A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
Win-San KhwaJia-Jing ChenJia-Fang LiXin SiEn-Yu YangXiaoyu SunRui LiuPai-Yu ChenQiang LiShimeng YuMeng-Fan ChangPublished in: ISSCC (2018)
Keyphrases
- learning algorithm
- memory space
- memory usage
- parallel implementation
- k means
- np hard
- segmentation algorithm
- parallel version
- memory requirements
- multiprocessor systems
- parallel processors
- parallel processing
- computational complexity
- parallel computation
- detection algorithm
- single processor
- low power
- massively parallel
- non binary
- power consumption
- external memory
- objective function