Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design.

Scott Zuloaga Rui Liu Pai-Yu Chen Shimeng Yu

Published in: ISCAS (2015)

Keyphrases

metal oxide semiconductor
semiconductor devices
high speed
silicon on insulator
integrated circuit
cmos technology
directed graph
multi layer
hidden nodes
decision trees
circuit design
application layer
shortest distance