A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.
Xin SiWin-San KhwaJia-Jing ChenJia-Fang LiXiaoyu SunRui LiuShimeng YuHiroyuki YamauchiQiang LiMeng-Fan ChangPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2019)
Keyphrases
- parallel processing
- multicore processors
- processing elements
- processing units
- shared memory
- single processor
- multithreading
- computing power
- parallel computing
- parallel programming
- distributed memory
- level parallelism
- parallel computers
- multiprocessor systems
- random access memory
- computational power
- parallel execution
- parallel computation
- parallel algorithm
- edge detection
- memory bandwidth
- data parallelism
- parallel processors
- parallel architectures
- parallel hardware
- multi core processors
- input image
- single instruction multiple data
- memory access
- parallel implementation
- edge information
- data transmission
- processor array
- massively parallel
- compute intensive
- computer architecture
- objective function
- edge detector
- weighted graph
- message passing interface
- load balance
- computing systems
- multi threaded
- memory requirements
- floating point
- memory subsystem
- high end
- inter processor communication