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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.

Hongwu JiangShanshi HuangXiaochen PengJian-Wei SuYen-Chi ChouWei-Hsing HuangTa-Wei LiuRuhui LiuMeng-Fan ChangShimeng Yu
Published in: DAC (2020)
Keyphrases
  • network on chip
  • network architecture
  • random access memory
  • power consumption
  • real time
  • massively parallel