Shyh-Shyuan Sheu

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 27

Top Topics

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. IEEE J. Solid State Circuits 59 (7) (2024)
Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang
CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. ISCAS (2024)
Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. IEEE J. Solid State Circuits 59 (1) (2024)
Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-Jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory. VLSI Technology and Circuits (2023)
Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. IEEE J. Solid State Circuits 58 (3) (2023)
Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs 70 (12) (2023)
Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. ISSCC (2023)
Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. ISSCC (2022)
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. IEEE J. Solid State Circuits 57 (2) (2022)
Ming-Chun Hong, Yao-Jen Chang, Yu-Chen Hsin, Liang-Ming Liu, Kuan-Ming Chen, Yi-Hui Su, Guan-Long Chen, Shan-Yi Yang, I-Jung Wang, Sk. Ziaur Rahaman, Hsin-Han Lee, Shih-Ching Chiu, Chen-Yi Shih, Chih-Yao Wang, Fang-Ming Chen, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Minn-Tsong Lin, Chih-I Wu, Tuo-Hung Hou
A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer. VLSI Technology and Circuits (2022)
Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, Ming-Ji Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, Shyh-Shyuan Sheu, Hung-Ming Chen, Kuan-Neng Chen, Wei-Chung Lo, Chih-I Wu
An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. VLSI Technology and Circuits (2022)
Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou
A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. A-SSCC (2021)
Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. ISSCC (2021)
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC (2020)
Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si, Ruhui Liu, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Je-Min Hung, Shyh-Shyuan Sheu, Sih-Han Li, Chih-I Wu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55 (10) (2020)
Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. DAC (2019)
Zhixiao Zhang, Jia-Jing Chen, Xin Si, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Yen-Cheng Chiu, Je-Min Hong, Shyh-Shyuan Sheu, Sih-Han Li, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. A-SSCC (2019)
Xin Si, He Qian, Meng-Fan Chang, Cheng-Xin Xue, Jian-Wei Su, Zhixiao Zhang, Sih-Han Li, Shyh-Shyuan Sheu, Heng-Yuan Lee, Ping-Cheng Chen, Huaqiang Wu
Circuit Design Challenges in Computing-in-Memory for AI Edge Devices. ASICON (2019)
Tsai-Kan Chien, Lih-Yih Chiou, Chi-Shian Chang, Jing-Yu Huang, Chung-Han Wu, Heng-Yuan Lee, Shyh-Shyuan Sheu
/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM. IEEE Trans. Circuits Syst. II Express Briefs (9) (2018)
Meng-Fan Chang, Chien-Chen Lin, Albert Lee, Yen-Ning Chiang, Chia-Chen Kuo, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu
A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing. IEEE J. Solid State Circuits 52 (6) (2017)
Tsai-Kan Chien, Lih-Yih Chiou, Yi-Sung Tsou, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu
Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches. ISLPED (2017)
Tsai-Kan Chien, Lih-Yih Chiou, Chieh-Wen Cheng, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu
Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture. APCCAS (2016)
Tsai-Kan Chien, Lih-Yih Chiou, Yao-Chun Chuang, Shyh-Shyuan Sheu, Heng-Yuan Li, Pei-Hua Wang, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu
A low store energy and robust ReRAM-based flip-flop for normally off microprocessors. ISCAS (2016)
Meng-Fan Chang, Ching-Hao Chuang, Yen-Ning Chiang, Shyh-Shyuan Sheu, Chia-Chen Kuo, Hsiang-Yun Cheng, John Sampson, Mary Jane Irwin
Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell. ISCAS (2016)
Tsai-Kan Chien, Lih-Yih Chiou, Shyh-Shyuan Sheu, Jing-Cian Lin, Chang-Chia Lee, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu
Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (2) (2016)
Meng-Fan Chang, Li-Yue Huang, Wen-Zhang Lin, Yen-Ning Chiang, Chia-Chen Kuo, Ching-Hao Chuang, Keng-Hao Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu
A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing. IEEE J. Solid State Circuits 51 (11) (2016)
Meng-Fan Chang, Shu-Meng Yang, Chia-Chen Kuo, Ting-Chin Yang, Che-Ju Yeh, Tun-Fei Chien, Li-Yue Huang, Shyh-Shyuan Sheu, Pei-Ling Tseng, Yu-Sheng Chen, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao
Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration Friendly Normally Off Applications. IEEE Trans. Circuits Syst. II Express Briefs (1) (2015)
Albert Lee, Meng-Fan Chang, Chien-Chen Lin, Chien-Fu Chen, Mon-Shu Ho, Chia-Chen Kuo, Pei-Ling Tseng, Shyh-Shyuan Sheu, Tzu-Kun Ku
RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications. VLSIC (2015)
Meng-Fan Chang, Albert Lee, Pin-Cheng Chen, Chrong Jung Lin, Ya-Chin King, Shyh-Shyuan Sheu, Tzu-Kun Ku
Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (2) (2015)
Meng-Fan Chang, Chien-Chen Lin, Albert Lee, Chia-Chen Kuo, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Pei-Ling Tseng, Heng-Yuan Lee, Tzu-Kun Ku
17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time. ISSCC (2015)
Meng-Fan Chang, Che-Wei Wu, Jui-Yu Hung, Ya-Chin King, Chomg-Jung Lin, Mon-Shu Ho, Chia-Cheng Kuo, Shyh-Shyuan Sheu
A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips. APCCAS (2014)
Li-Yue Huang, Meng-Fan Chang, Ching-Hao Chuang, Chia-Chen Kuo, Chien-Fu Chen, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Keng-Li Su, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao
ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing. VLSIC (2014)
Wen-Pin Lin, Shyh-Shyuan Sheu, Chia-Chen Kuo, Pei-Ling Tseng, Meng-Fan Chang, Keng-Li Su, Chih-Sheng Lin, Kan-Hsueh Tsai, Sih-Han Lee, Szu-Chieh Liu, Yu-Sheng Chen, Heng-Yuan Lee, Ching-Chih Hsu, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao
A nonvolatile look-up table using ReRAM for reconfigurable logic. A-SSCC (2014)
Meng-Fan Chang, Chia-Chen Kuo, Shyh-Shyuan Sheu, Chorng-Jung Lin, Ya-Chin King, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Jui-Jen Wu, Yu-Der Chih
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme. IEEE J. Solid State Circuits 49 (4) (2014)
Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu, Yih-Shan Yang, Yu-Sheng Chen, Heng-Yuan Lee, Chen-Hsin Lien, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. IEEE J. Solid State Circuits 48 (3) (2013)
Meng-Fan Chang, Chih-Sheng Lin, Wei-Cheng Wu, Ming-Pin Chen, Yen-Huei Chen, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, Cha-Hsin Lin, Hiroyuki Yamauchi
A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms. IEEE J. Solid State Circuits 48 (6) (2013)
Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Yu-Sheng Chen, Pang-Shiu Chen, Ming-Jinn Tsai, Yu-Lung Lo
A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit. IEICE Trans. Electron. (6) (2012)
Meng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen, Hiroyuki Yamauchi, Pi-Feng Chiu, Shyh-Shyuan Sheu
Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device. ASP-DAC (2012)
Pi-Feng Chiu, Meng-Fan Chang, Che-Wei Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu, Yu-Sheng Chen, Ming-Jinn Tsai
Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications. IEEE J. Solid State Circuits 47 (6) (2012)
Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Meng-Fan Chang, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Frederick T. Chen, Ming-Jinn Tsai
Fast-Write Resistive RAM (RRAM) for Embedded Applications. IEEE Des. Test Comput. 28 (1) (2011)
Frederick T. Chen, Heng-Yuan Lee, Yu-Sheng Chen, Yenya Hsu, Lijie Zhang, Pang-Shiu Chen, Weisu Chen, Peiyi Gu, Wenhsing Liu, Sumin Wang, Chen-Han Tsai, Shyh-Shyuan Sheu, Ming-Jinn Tsai, Ru Huang
Resistance switching for RRAM applications. Sci. China Inf. Sci. 54 (5) (2011)
Shyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. ISSCC (2011)
Meng-Fan Chang, Pi-Feng Chiu, Shyh-Shyuan Sheu
Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC. ASP-DAC (2011)
Meng-Fan Chang, Pi-Feng Chiu, Wei-Cheng Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu
Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM). ASICON (2011)
Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu
Training-based forming process for RRAM yield improvement. VTS (2011)
Meng-Hsueh Chiang, Yi-Bo Liao, Jun-Tin Lin, Wei-Chou Hsu, Chu Yu, Pei-Chia Chiang, Y.-Y. Hsu, W.-H. Liu, Shyh-Shyuan Sheu, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai
Low power design of phase-change memory based on a comprehensive model. IET Comput. Digit. Tech. 4 (4) (2010)
Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, Shyh-Shyuan Sheu
A CMOS low power voltage controlled oscillator with split-path controller. ICECS (2001)