Yu-Lung Lo

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 9

Top Topics

Design Considerations

Surface Roughness

Top Venues

Circuits Syst. Signal Process.

IEEE Robotics Autom. Lett.

IEEE Trans. Instrum. Meas.

Publications

Chieh-Chen Tsai, Yu-Lung Lo, Ching-Min Chang, Po-Ling Huang
Characterization of Mean Absorbance of Anisotropic Turbid Media Using Stokes-Mueller Matrix Polarimetry Approach. IEEE Trans. Instrum. Meas. 72 (2023)
Hong-Chuong Tran, Yu-Lung Lo, Haw Ching Yang, Hung-Chang Hsiao, Fan-Tien Cheng, Tsung-Han Kuo
Intelligent Additive Manufacturing Architecture for Enhancing Uniformity of Surface Roughness and Mechanical Properties of Laser Powder Bed Fusion Components. IEEE Trans Autom. Sci. Eng. 20 (4) (2023)
Chen-Kuei Chung, You-Jun Huang, Tun-Kai Wang, Yu-Lung Lo
Fiber-Based Triboelectric Nanogenerator for Mechanical Energy Harvesting and Its Application to a Human-Machine Interface. Sensors 22 (24) (2022)
Haw Ching Yang, Muhammad Adnan, Chih-Hung Huang, Fan-Tien Cheng, Yu-Lung Lo, Chih-Hua Hsu
An Intelligent Metrology Architecture With AVM for Metal Additive Manufacturing. IEEE Robotics Autom. Lett. 4 (3) (2019)
Hsiu-An Tsai, Yu-Lung Lo
An Approach to Measure Tilt Motion, Straightness and Position of Precision Linear Stage with a 3D Sinusoidal-Groove Linear Reflective Grating and Triangular Wave-Based Subdivision Method. Sensors 19 (12) (2019)
Tseng-Lin Chen, Quoc-Hung Phan, Yu-Lung Lo
Mueller Optical Coherence Tomophraphy Technique for Non-Invasive Glucose Monitoring. PHOTOPTICS (2018)
Yu-Lung Lo, Wei-Hsiang Ho
A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems. Circuits Syst. Signal Process. 36 (12) (2017)
Wei-Bin Yang, Yu-Yao Lin, Yu-Lung Lo
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input. Circuits Syst. Signal Process. 36 (12) (2017)
Yu-Lung Lo, Yi-Hsuan Chuang
A High-Efficiency CMOS Rectifier with Wide Harvesting Range and Wide Band Based on MPPT Technique for Low-Power IoT System Applications. Circuits Syst. Signal Process. 36 (12) (2017)
Wei-Bin Yang, Yu-Yao Lin, Chi-Hsiung Wang, Kuo-Ning Chang, Cing-Huan Chen, Yu-Lung Lo
Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18µm CMOS process. ISPACS (2015)
Yu-Lung Lo, Jhih-Wei Tsai
A low-area full-division-range programmable frequency divider with a 50% duty-cycle output. Microelectron. J. 44 (2) (2013)
Yu-Lung Lo, Jhih-Wei Tsai, Han-Ying Liu, Wei-Bin Yang
A GHz full-division-range programmable divider with output duty-cycle improved. DDECS (2013)
Yu-Lung Lo, Wei-Jen Chen
A 0.7 V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35 μm CMOS technology. Microelectron. J. 43 (11) (2012)
Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Yu-Sheng Chen, Pang-Shiu Chen, Ming-Jinn Tsai, Yu-Lung Lo
A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit. IEICE Trans. Electron. (6) (2012)
Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, Jing-Shiuan Huang
A 0.5-V 0.4-2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2011)
Wei-Bin Yang, Yu-Lung Lo, Ting-Sheng Chao
Clock Generator with 50% Duty Cycle Output. IEICE Trans. Electron. (3) (2010)
Yu-Lung Lo, Ling-Yi Tsai
Approximate Searching for Music Data in Real-Valued Feature Indexing. J. Convergence Inf. Technol. 4 (4) (2009)
Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng
Designing ultra-low voltage PLL Using a bulk-driven technique. ESSCIRC (2009)
Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. IEEE Trans. Circuits Syst. II Express Briefs (5) (2009)
Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Trans. Electron. (6) (2009)
Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, Kuo-Hsing Cheng
Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2009)
Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS (2008)
Kuo-Hsing Cheng, Pei-Kai Tseng, Yu-Lung Lo
A Phase Interpolator For Sub-1V And High Frequency For Clock And Data Recovery. ICECS (2007)
Kuo-Hsing Cheng, Yu-Lung Lo, Ching-Wen Lai, Wei-Bin Yang
A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique. ICECS (2007)
Kuo-Hsing Cheng, Yu-Lung Lo
A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator. IEEE Trans. Circuits Syst. II Express Briefs (7) (2007)
Ting-Sheng Jau, Wei-Bin Yang, Yu-Lung Lo
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler. ICECS (2006)
Cihun-Siyong Alex Gong, Chen-Lung Wu, Sheng-Yang Ho, Tong-Yi Chen, Jia-Chun Huang, Chia-Wei Su, Chun-Hsien Su, Yin Chang, Kuo-Hsing Cheng, Yu-Lung Lo, Muh-Tian Shiue
Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem. ICECS (2006)
Kuo-Hsing Cheng, Yu-Lung Lo
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. DATE Designers' Forum (2006)
Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng
A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. ISCAS (2006)
Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo, Chia-Wei Su
A phase-detect synchronous mirror delay for clock skew-compensation circuits. ISCAS (2) (2005)
Kuo-Hsing Cheng, Yu-Lung Lo
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. ESSCIRC (2005)
Kuo-Hsing Cheng, Yu-Lung Lo
A fast-lock DLL with power-on reset circuit. ISCAS (4) (2004)
Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu
A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. ISCAS (2) (2003)
Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung
A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. IWSOC (2003)
Yu-Lung Lo, Chih-Chiang Tsao
Wirebond profiles characterized by a modified linkage-spring model which includes a looping speed factor. Microelectron. Reliab. 42 (2) (2002)