Yu-Chang Tsai

Publication Activity (10 Years)

Years Active: 2008-2011
Publications (10 Years): 0

Publications

Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, Jing-Shiuan Huang
A 0.5-V 0.4-2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2011)
Yu-Chang Tsai, Kuo-Hsing Cheng, Yen-Hsueh Wu, Ying-Fu Lin
A CMOS adaptive equalizer using low-voltage zero generators technique. ESSCIRC (2010)
Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, Ying-Fu Lin
A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications. IEEE Trans. Circuits Syst. II Express Briefs (5) (2010)
Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Trans. Electron. (7) (2009)
Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu
A low jitter self-calibration PLL for 10Gbps SoC transmission links application. ICECS (2008)