Kuo-Hsing Cheng

ORCID

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 13

Top Venues

DDECS

ICECS

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Kuo-Hsing Cheng, Chun-Yao Chang, Hong-Yi Huang, Yun-Teng Shih
A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System. ICECS (2023)
Hong-Yi Huang, Yu-Ming Tsao, Angelo Nico M. Daroy, Kuo-Hsing Cheng
A 1~50mA 20ns Settling Time Low Dropout Regulator. ICECS (2023)
Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng
A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications. IEEE Trans. Very Large Scale Integr. Syst. 29 (10) (2021)
Tsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng
A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System. DDECS (2019)
Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2018)
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang
Low supply voltage and multiphase all-digital crystal-less clock generator. IET Circuits Devices Syst. 12 (6) (2018)
Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng
A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application. ISCAS (2018)
Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering. VLSI-DAT (2017)
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture. IEICE Trans. Electron. (6) (2016)
Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang
A chaotically injected timing technique for ring-based oscillators. DDECS (2016)
Hong-Yi Huang, Kun-Yuan Chen, Jia-Hao Xie, Ming-Ta Lee, Hao-Chiao Hong, Kuo-Hsing Cheng
Gm-C filter with automatic calibration scheme. DDECS (2016)
Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng
Low-voltage indoor energy harvesting using photovoltaic cell. DDECS (2016)
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. IEICE Electron. Express 13 (2) (2016)
Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang
A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. DDECS (2015)
Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou
PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. DDECS (2015)
Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang
A low supply voltage synchronous mirror delay with quadrature phase output. DDECS (2014)
Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng
A 64-MHz∼640-MHz 64-phase clock generator. DDECS (2014)
Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun
A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes. IEEE Trans. Circuits Syst. II Express Briefs (8) (2014)
Hong-Yi Huang, Chinet Otic Mocorro, Julyver Pinaso, Kuo-Hsing Cheng
Indoor energy harvesting using photovoltaic cell for battery recharging. DDECS (2013)
Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang
A low jitter delay-locked-loop applied for DDR4. DDECS (2013)
Hong-Yi Huang, Cheng-Yu Chen, Kuo-Hsing Cheng
External capacitorless low dropout linear regulator using cascode structure. DDECS (2013)
Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, Bo-Qian Jiang
An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Yu-Sheng Chen, Pang-Shiu Chen, Ming-Jinn Tsai, Yu-Lung Lo
A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit. IEICE Trans. Electron. (6) (2012)
Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng
Auto-calibration techniques in built-in jitter measurement circuit. DDECS (2012)
Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, Kuo-Hsing Cheng
A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology. ISCAS (2012)
Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang
A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo
All digital phase-locked loop using active inductor oscillator and novel locking algorithm. ISCAS (2011)
Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Meng-Fan Chang, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Frederick T. Chen, Ming-Jinn Tsai
Fast-Write Resistive RAM (RRAM) for Embedded Applications. IEEE Des. Test Comput. 28 (1) (2011)
Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-hao Fan, Chi-Yang Chang
A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation. ESSCIRC (2011)
Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, Jing-Shiuan Huang
A 0.5-V 0.4-2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2011)
Shyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. ISSCC (2011)
Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu
A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. IEEE Trans. Circuits Syst. II Express Briefs (8) (2011)
Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang
A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique. IEEE J. Solid State Circuits 46 (5) (2011)
Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang
A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS (2010)
Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng
A 3 GHz DLL-based clock generator with stuck locking protection. ICECS (2010)
Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, Chien-Cheng Chen
A loading effect insensitive and high precision clock synchronization circuit. ESSCIRC (2010)
Yu-Chang Tsai, Kuo-Hsing Cheng, Yen-Hsueh Wu, Ying-Fu Lin
A CMOS adaptive equalizer using low-voltage zero generators technique. ESSCIRC (2010)
Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, Ying-Fu Lin
A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications. IEEE Trans. Circuits Syst. II Express Briefs (5) (2010)
Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Trans. Electron. (7) (2009)
Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng
Designing ultra-low voltage PLL Using a bulk-driven technique. ESSCIRC (2009)
Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. IEEE Trans. Circuits Syst. II Express Briefs (5) (2009)
Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Trans. Electron. (6) (2009)
Shu-Yu Jiang, Kuo-Hsing Cheng, Pei-Yi Jian
A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver. IEEE Trans. Very Large Scale Integr. Syst. 17 (12) (2009)
Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, Kuo-Hsing Cheng
Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2009)
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
0.5V 160-MHz 260uW all digital phase-locked loop. DDECS (2009)
Kuo-Hsing Cheng, Chia-Wei Su, Hsin-Hsin Ko
Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing. IEICE Trans. Electron. (12) (2008)
Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS (2008)
Kuo-Hsing Cheng, Chia-Wei Su, Kai-Fei Chang
A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation. IEEE J. Solid State Circuits 43 (2) (2008)
Cihun-Siyong Alex Gong, Ci-Tong Hong, Kai-Wen Yao, Muh-Tian Shiue, Kuo-Hsing Cheng
A compact and low-power SRAM with improved read static noise margin. ICECS (2008)
Kuo-Hsing Cheng, Chia-Wei Su, Hsin-Hsin Ko
A high-accuracy and high-efficiency on-chip current sensing for current-mode control CMOS DC-DC buck converter. ICECS (2008)
Kuo-Hsing Cheng, Hsin-Hao Wang, Ding-Jyun Huang
A 1-V 10-bit 2GSample/s D/A converter based on precision current reference in 90-nm CMOS. ICECS (2008)
Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu
A low jitter self-calibration PLL for 10Gbps SoC transmission links application. ICECS (2008)
Kuo-Hsing Cheng, Chia-Wei Su, Meng-Jhe Wu, Yu-Ling Chang
A wide-range DLL-based clock generator with phase error calibration. ICECS (2008)
Kuo-Hsing Cheng, Pei-Kai Tseng, Yu-Lung Lo
A Phase Interpolator For Sub-1V And High Frequency For Clock And Data Recovery. ICECS (2007)
Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su
A Sub-1V Low-Power High-Speed Static Frequency Divider. ISCAS (2007)
Kuo-Hsing Cheng, Yu-Lung Lo, Ching-Wen Lai, Wei-Bin Yang
A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique. ICECS (2007)
Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng
All-Digital PLL Using Pulse-Based DCO. ICECS (2007)
Kuo-Hsing Cheng, Yu-Lung Lo
A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator. IEEE Trans. Circuits Syst. II Express Briefs (7) (2007)
Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang
A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay. ICECS (2006)
Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang
Self-sampled vernier delay line for built-in clock jitter measurement. ISCAS (2006)
Cihun-Siyong Alex Gong, Chen-Lung Wu, Sheng-Yang Ho, Tong-Yi Chen, Jia-Chun Huang, Chia-Wei Su, Chun-Hsien Su, Yin Chang, Kuo-Hsing Cheng, Yu-Lung Lo, Muh-Tian Shiue
Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem. ICECS (2006)
Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee
64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics. J. Circuits Syst. Comput. 15 (1) (2006)
Kuo-Hsing Cheng, Yu-Lung Lo
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. DATE Designers' Forum (2006)
Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng
A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. ISCAS (2006)
Kuo-Hsing Cheng, Shun-Wen Cheng
Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications. J. Inf. Sci. Eng. 22 (4) (2006)
Wei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng
The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. ECCTD (2005)
Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo, Chia-Wei Su
A phase-detect synchronous mirror delay for clock skew-compensation circuits. ISCAS (2) (2005)
Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) (2005)
Kuo-Hsing Cheng, Shun-Wen Cheng
64-Bit High-Performance Power-Aware Conditional Carry Adder Design. IEICE Trans. Electron. (6) (2005)
Kuo-Hsing Cheng, Yu-Lung Lo
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. ESSCIRC (2005)
Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang
64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. IWSOC (2004)
Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. ISCAS (1) (2004)
Kuo-Hsing Cheng, Yu-Lung Lo
A fast-lock DLL with power-on reset circuit. ISCAS (4) (2004)
Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. ISVLSI (2004)
Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang
Static divided word matching line for low-power Content Addressable Memory design. ISCAS (2) (2004)
Kuo-Hsing Cheng, Tsung-Shen Chen, Chia Ming Tu
A 14-bit, 200 MS/s digital-to-analog converter without trimming. ISCAS (1) (2004)
Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu
A Robust Handshake for Asynchronous System. IWSOC (2003)
Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang
A new robust handshake for asymmetric asynchronous micro-pipelines. ISCAS (5) (2003)
Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen
BIST for clock jitter measurements. ISCAS (5) (2003)
Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu
A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. ISCAS (2) (2003)
Kuo-Hsing Cheng, Yung-Hsiang Lin
A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. ISCAS (5) (2003)
Kuo-Hsing Cheng, Chung-Yu Chang, Chia-Hung Wei
A CMOS charge pump for sub-2.0 V operation. ISCAS (5) (2003)
Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung
A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. IWSOC (2003)
Kuo-Hsing Cheng, Wei-Bin Yang, Cheng-Ming Ying
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop. IEEE Trans. Circuits Syst. II Express Briefs 50 (11) (2003)
Kuo-Hsing Cheng, Shun-Wen Cheng
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. VLSI Design (2002)
Kuo-Hsing Cheng, Shun-Wen Cheng
Influences of minimum cut plane properties on the mincut circuit partitioning problems. ICECS (2002)
Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung
A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) (2001)
Shun-Wen Cheng, Kuo-Hsing Cheng
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning. ISCAS (5) (2001)
Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang, Wei-Bin Yang
A difference detector PFD for low jitter PLL. ICECS (2001)
Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, Shyh-Shyuan Sheu
A CMOS low power voltage controlled oscillator with split-path controller. ICECS (2001)
Kuo-Hsing Cheng, Shun-Wen Cheng
A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning. ICECS (2001)
Kuo-Hsing Cheng, Chi-Che Chen, Chun-Fu Chung
Accurate current mirror with high output impedance. ICECS (2001)
Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang
A 1.2 V 500 MHz 32-bit carry-lookahead adder. ICECS (2001)
Kuo-Hsing Cheng, Chih-Sheng Huang, Chun-Pin Lin
The design and implementation of DCT/IDCT chip with novel architecture. ISCAS (2000)
Kuo-Hsing Cheng, Chih-Sheng Huang
The novel efficient design of XOR/XNOR function for adder applications. ICECS (1999)
Kuo-Hsing Cheng, Wei-Bin Yang
The suggestion for CFS CMOS buffer. ICECS (1999)
Kuo-Hsing Cheng, Yu-Kwang Yeha, Farn-Sou Lian
Low voltage low power high-speed BiCMOS multiplier. ICECS (1998)
Kuo-Hsing Cheng, Yu-Yee Liow
A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic. ICECS (1996)

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Publication Activity (10 Years)

Top Topics

Top Venues

Kuo-Hsing Cheng