Yuh-Kuang Tseng

Publication Activity (10 Years)

Years Active: 1994-2007
Publications (10 Years): 0

Publications

Yuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. SoCC (2007)
Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng
A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. ISCAS (2006)
Yuh-Kuang Tseng, Chung-Yu Wu
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications. IEEE J. Solid State Circuits 34 (1) (1999)
Yuh-Kuang Tseng, Chung-Yu Wu
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications. IEEE J. Solid State Circuits 33 (10) (1998)
Chung-Yu Wu, Yuh-Kuang Tseng
M-BiCMOS) logic for low-voltage applications. ICECS (1996)
Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu
Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit. ISCAS (1994)