Ming-Dou Ker

ORCID

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 38

Top Venues

IEEE Trans. Biomed. Circuits Syst.

VLSI-DAT

Microelectron. Reliab.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Chi-Wei Huang, Chin-Kai Lai, Chung-Chih Hung, Chung-Yu Wu, Ming-Dou Ker
A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (6) (2023)
Chao-Yang Ke, Yu-Chia Tsui, Bing-Yue Tsui, Ming-Dou Ker
Investigation of Safe Operating Area on 4H-SiC 600V VDMOSFET with TLP and UIS Test Methods. IRPS (2023)
Chia-Chi Hsieh, Yi-Hui Wu, Ming-Dou Ker
Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-Modulation. IEEE Trans. Biomed. Circuits Syst. 17 (2) (2023)
I-Hsuan Wu, Ming-Dou Ker
Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control. VLSI-DAT (2022)
Han-Sheng Huang, Ming-Dou Ker
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events. VLSI-DAT (2021)
Chao-Yang Chen, Jian-Hsing Lee, Karuna Nidhi, Tzer-Yaa Bin, Geeng-Lih Lin, Ming-Dou Ker
Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. IRPS (2021)
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Li-Yang Tang, Yen-Fu Tu, Po-Chih Chang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification. IEEE J. Solid State Circuits 56 (10) (2021)
Chia-Chi Hsieh, Ming-Dou Ker
Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process. IEEE Trans. Biomed. Circuits Syst. 15 (3) (2021)
Shane Harrigan, Sonya A. Coleman, Ming-Dou Ker, Pratheepan Yogarajah, Zheng Fang, Chengdong Wu
ROT-Harris: A Dynamic Approach to Asynchronous Interest Point Detection. MVA (2021)
Shiau-Pin Lin, Ming-Dou Ker
Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation. IEEE Trans. Circuits Syst. (11) (2020)
Yi-Hui Wu, Yi-Huan Ou-Yang, Chiung-Chu Chen, Chen-Yi Lee, Chung-Yu Wu, Ming-Dou Ker
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals. EMBC (2020)
Chao-Yang Ke, Ming-Dou Ker
Over-Voltage Protection on the CC Pin of USB Type-C Interface against Electrical Overstress Events. IRPS (2020)
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition. A-SSCC (2020)
Ting-Yang Yen, Ming-Dou Ker
Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications. IEEE Trans. Biomed. Circuits Syst. 14 (5) (2020)
Chun-Cheng Chen, Ming-Dou Ker
Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process. IRPS (2019)
Tao-Yi Hung, Ming-Dou Ker
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications. ISCAS (2019)
Ming-Dou Ker, Maurizio Valle, Matthew L. Johnston
Guest Editorial: Special Issue on Selected Papers From IEEE ISCAS 2019. IEEE Trans. Biomed. Circuits Syst. 13 (6) (2019)
Zhicong Luo, Li-Chin Yu, Ming-Dou Ker
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Chi-Wei Liu, Yi-Lun Chen, Pei-Chun Liao, Shiau-Pin Lin, Ting-Wei Wang, Ming-Jie Chung, Po-Hung Chen, Ming-Dou Ker, Chung-Yu Wu
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS. IEEE Trans. Circuits Syst. II Express Briefs (5) (2019)
Xin-Hong Qian, Yi-Chung Wu, Tzu-Yi Yang, Cheng-Hsiang Cheng, Hsing-Chien Chu, Wan-Hsueh Cheng, Ting-Yang Yen, Tzu-Han Lin, Yung-Jen Lin, Yu-Chi Lee, Jia-Heng Chang, Shih-Ting Lin, Shang-Hsuan Li, Tsung-Chen Wu, Chien-Chang Huang, Sung-Hao Wang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Tai-Shih Chi, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem. IEEE Trans. Biomed. Eng. 66 (11) (2019)
Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, Tzu-Han Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, Yue-Loong Hsin, Chen-Yi Lee, Ming-Dou Ker, Chung-Yu Wu
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control. IEEE J. Solid State Circuits 53 (11) (2018)
Wen-Chieh Chen, Ming-Dou Ker
Surge protection design with surge-to-digital converter for microelectronic circuits and systems. Microelectron. Reliab. (2018)
Shiau-Pin Lin, Ming-Dou Ker
Design of Multiple-Charge-Pump System for Implantable Biomedical Applications. BioCAS (2018)
Zhicong Luo, Ming-Dou Ker
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (2) (2018)
Chia-Chi Hsieh, Ming-Dou Ker
Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications. MWSCAS (2018)
Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan
An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation. IEICE Trans. Electron. (8) (2017)
Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Jen-Chieh Liu, Yu Lee
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2017)
Zhicong Luo, Ming-Dou Ker, Wan-Hsueh Cheng, Ting-Yang Yen
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2017)
Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw
Design considerations and clinical applications of closed-loop neural disorder control SoCs. ASP-DAC (2017)
Zhicong Luo, Ming-Dou Ker, Tzu-Yi Yang, Wan-Hsueh Cheng
A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process. IEEE Trans. Biomed. Circuits Syst. 11 (5) (2017)
Chun-Yu Lin, Rui-Hong Liu, Ming-Dou Ker
Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process. Microelectron. Reliab. 78 (2017)
Zhicong Luo, Ming-Dou Ker
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process. IEEE Trans. Biomed. Circuits Syst. 10 (6) (2016)
Jie-Ting Chen, Chun-Yu Lin, Rong-Kun Chang, Ming-Dou Ker, Tzu-Chien Tzeng, Tzu-Chiang Lin
ESD protection design for high-speed applications in CMOS technology. MWSCAS (2016)
Zhicong Luo, Ming-Dou Ker
Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator. NEWCAS (2016)
Chia-Tsen Dai, Ming-Dou Ker
ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC. SoCC (2015)
Federico A. Altolaguirre, Ming-Dou Ker
Active ESD protection for input transistors in a 40-nm CMOS process. VLSI-DAT (2015)
Seian-Feng Liao, Kai-Neng Tang, Ming-Dou Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. ECCTD (2015)
Hui-Wen Tsai, Ming-Dou Ker
Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits. ECCTD (2015)
Ming-Dou Ker, Wan-Yen Lin, Cheng-Cheng Yen
SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance. Microelectron. Reliab. 54 (1) (2014)
Li-Wei Chu, Chun-Yu Lin, Ming-Dou Ker, Ming-Hsiang Song, Jeng-Chou Tseng, Chewnpu Jou, Ming-Hsien Tsai
ESD protection design for wideband RF applications in 65-nm CMOS process. ISCAS (2014)
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. IEEE J. Solid State Circuits 49 (1) (2014)
Federico A. Altolaguirre, Ming-Dou Ker
Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process. MWSCAS (2014)
Kuan-Yu Lin, Ming-Dou Ker, Chun-Yu Lin
A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. ISCAS (2014)
Po-Yen Chiu, Ming-Dou Ker
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit. Microelectron. Reliab. 54 (1) (2014)
Che-Hao Chuang, Ming-Dou Ker
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection. IEEE Trans. Ind. Electron. 61 (10) (2014)
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Jin-Chern Chiou, Chih-Wei Chang, Lei-Chun Chou, Chung-Yu Wu
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control. ISSCC (2013)
Chun-Yu Lin, Wei-Ling Chen, Ming-Dou Ker
Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability. IEEE Trans. Biomed. Circuits Syst. 7 (2) (2013)
Po-Yen Chiu, Ming-Dou Ker
Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology. SoCC (2013)
Federico A. Altolaguirre, Ming-Dou Ker
Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. VLSI-DAT (2013)
Hui-Wen Tsai, Ming-Dou Ker, Yi-Sheng Liu, Ming-Nan Chuang
Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits. VLSI-DAT (2013)
Federico A. Altolaguirre, Ming-Dou Ker
Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology. ISCAS (2013)
Chih-Ting Yeh, Ming-Dou Ker
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit. Microelectron. Reliab. 53 (2) (2013)
Ming-Dou Ker, Po-Yen Chiu
Thin-Oxide Devices. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2013)
Chih-Ting Yeh, Ming-Dou Ker
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. VLSI-DAT (2013)
Shiang-Yu Tsai, Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker
Design of ESD protection for RF CMOS power amplifier with inductor in matching network. APCCAS (2012)
Chih-Ting Yeh, Ming-Dou Ker
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. VLSI-DAT (2012)
Chun-Yu Lin, Yi-Ju Li, Ming-Dou Ker
High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process. NEWCAS (2012)
Chun-Yu Lin, Tang-Long Chang, Ming-Dou Ker
Investigation on CDM ESD events at core circuits in a 65-nm CMOS process. Microelectron. Reliab. 52 (11) (2012)
Ming-Dou Ker, Wei-Ling Chen, Chun-Yu Lin
Live demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability. BioCAS (2012)
Ming-Dou Ker, Cheng-Cheng Yen
New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels. IEEE Trans. Ind. Electron. 59 (2) (2012)
Chih-Ting Yeh, Ming-Dou Ker
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications. Microelectron. Reliab. 52 (6) (2012)
Li-Wei Chu, Chun-Yu Lin, Shiang-Yu Tsai, Ming-Dou Ker, Ming-Hsiang Song, Chewnpu Jou, Tse-Hua Lu, Jeng-Chou Tseng, Ming-Hsien Tsai, Tsun-Lai Hsu, Ping-Fang Hung, Tzu-Heng Chang
Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. ISCAS (2012)
Ya-Chun Huang, Ming-Dou Ker, Chun-Yu Lin
Design of negative high voltage generator for biphasic stimulator with soc integration consideration. BioCAS (2012)
Chih-Ting Yeh, Ming-Dou Ker
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs (3) (2012)
Ming-Dou Ker, Wan-Yen Lin
New design of transient-noise detection circuit with SCR device for system-level ESD protection. NEWCAS (2012)
Yi-Hsin Weng, Hui-Wen Tsai, Ming-Dou Ker
Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process. Microelectron. Reliab. 51 (5) (2011)
Ming-Dou Ker, Wen-Yi Chen, Wuu-Trong Shieh, I-Ju Wei
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs. IEEE J. Solid State Circuits 46 (2) (2011)
Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process. Microelectron. Reliab. 51 (8) (2011)
Chun-Yu Lin, Li-Wei Chu, Shiang-Yu Tsai, Ming-Dou Ker, Tse-Hua Lu, Tsun-Lai Hsu, Ping-Fang Hung, Ming-Hsiang Song, Jeng-Chou Tseng, Tzu-Heng Chang, Ming-Hsien Tsai
Modified LC-tank ESD protection design for 60-GHz RF applications. ECCTD (2011)
Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. ISCAS (2011)
Ming-Dou Ker, Che-Lun Hsu, Wen-Yi Chen
ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. ISCAS (2010)
Chun-Yu Lin, Ming-Dou Ker
2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. ISCAS (2010)
Ming-Dou Ker, Cheng-Cheng Yen
New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance. IEEE Trans. Ind. Electron. 57 (10) (2010)
Shih-Hung Chen, Ming-Dou Ker
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology. Microelectron. Reliab. 50 (6) (2010)
Hui-Wen Tsai, Ming-Dou Ker
Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation. Microelectron. Reliab. 50 (1) (2010)
Chun-Yu Lin, Ming-Dou Ker, Yuan-Wen Hsiao
Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme. Microelectron. Reliab. 50 (6) (2010)
Wen-Yi Chen, Ming-Dou Ker
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2010)
Chih-Ting Yeh, Ming-Dou Ker
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. IEEE J. Solid State Circuits 45 (11) (2010)
Ming-Dou Ker, Chang-Tzu Wang
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS. CICC (2009)
Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process. ISCAS (2009)
Chang-Tzu Wang, Ming-Dou Ker
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology. IEEE J. Solid State Circuits 44 (3) (2009)
Shih-Hung Chen, Ming-Dou Ker
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs (5) (2009)
Ming-Dou Ker, Yan-Liang Lin
Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices. CICC (2009)
Yuan-Wen Hsiao, Ming-Dou Ker
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process. Microelectron. Reliab. 49 (6) (2009)
Wen-Yi Chen, Ming-Dou Ker, Yeh-Ning Jou, Yeh-Jen Huang, Geeng-Lih Lin
Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection. ISCAS (2009)
Tzu-Ming Wang, Ming-Dou Ker, Hung-Tai Liao
Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2009)
Ming-Dou Ker, Yuan-Wen Hsiao
Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits. IEICE Trans. Electron. (3) (2009)
Tzu-Ming Wang, Yu-Hsuan Li, Ming-Dou Ker
On-glass digital-to-analog converter with gamma correction for panel data driver. ICECS (2008)
Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang, Yeh-Ning Jou, Geeng-Lih Lin
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration. APCCAS (2008)
Shih-Hung Chen, Ming-Dou Ker
Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology. ICECS (2008)
Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu
Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process. CICC (2008)
Chun-Yu Lin, Ming-Dou Ker, Guo-Xuan Meng
Low-Capacitance and Fast Turn-on SCR for RF ESD Protection. IEICE Trans. Electron. (8) (2008)
Yuan-Wen Hsiao, Ming-Dou Ker
An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process. CICC (2008)
Ming-Dou Ker, Tzu-Ming Wang, Hung-Tai Liao
2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue. ISCAS (2008)
Ming-Dou Ker, Tzu-Ming Wang, Fang-Ling Hu
Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process. ICECS (2008)
Ming-Dou Ker, Cheng-Cheng Yen
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test. IEEE J. Solid State Circuits 43 (11) (2008)
Jung-Sheng Chen, Ming-Dou Ker
Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process. IEICE Trans. Electron. (3) (2008)
Ming-Dou Ker, Chun-Yu Lin, Guo-Xuan Meng
ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. ISCAS (2008)
Shih-Hung Chen, Ming-Dou Ker
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits. Microelectron. Reliab. 47 (9-11) (2007)
Ming-Dou Ker, Wei-Jen Chang
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology. Microelectron. Reliab. 47 (1) (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

Ming-Dou Ker