Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection.
Chih-Ting YehMing-Dou KerPublished in: IEEE J. Solid State Circuits (2010)
Keyphrases
- high speed
- power dissipation
- chip design
- circuit design
- short circuit
- evolvable hardware
- power consumption
- ibm power processor
- analog vlsi
- low power
- micron cmos
- cmos technology
- digital circuits
- single chip
- power supply
- printed circuit boards
- transmission line
- single phase
- low voltage
- power reduction
- memory subsystem
- duty cycle
- design methodology
- low cost