Chih-Ting Yeh

Publication Activity (10 Years)

Years Active: 2008-2023
Publications (10 Years): 6

Top Topics

Speaker Recognition

Polarity Classification

Convolutional Neural Network

Passage Retrieval

Top Venues

Publications

Chia-Ying Tsao, Chih-Ting Yeh, Jyh-Shing Roger Jang, Yung-Yaw Chen, Chuan-Ju Wang
Multi-behavior Recommendation with Action Pattern-aware Networks. WI/IAT (2023)
Jia-Huei Ju, Chih-Ting Yeh, Cheng-Wei Lin, Chia-Ying Tsao, Jun-En Ding, Chuan-Ju Wang, Ming-Feng Tsai
An Exploration Study of Multi-stage Conversational Passage Retrieval: Paraphrase Query Expansion and Multi-view Point-wise Ranking. TREC (2021)
Chih-Ting Yeh, Zhe-Li Lin, Sheng-Chieh Lin, Jing-Kai Lou, Ming-Feng Tsai, Chuan-Ju Wang
A Learning Framework with Disposable Auxiliary Networks for Early Prediction of Product Success. WI/IAT (2021)
Chia-Ping Chen, Su-Yu Zhang, Chih-Ting Yeh, Jia-Ching Wang, Tenghui Wang, Chien-Lin Huang
Speaker Characterization Using TDNN-LSTM Based Speaker Embedding. ICASSP (2019)
Chih-Ting Yeh, Po-Chin Wang, Su-Yu Zhang, Chia-Ping Chen, Shan-Wen Hsiao, Bo-Cheng Chan, Chung-Li Lu
以三元組損失微調時延神經網路語者嵌入函數之語者辨識系統(Time Delay Neural Network-based Speaker Embedding Function Fine-tuned with Triplet Loss for Distance-based Speaker Recognition). ROCLING (2019)
Chih-Ting Yeh, Chia-Ping Chen
結合卷積神經網路與遞迴神經網路於推文極性分類 (Combining Convolutional Neural Network and Recurrent Neural Network for Tweet Polarity Classification) [In Chinese]. ROCLING (2018)
Chih-Ting Yeh, Ming-Dou Ker
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit. Microelectron. Reliab. 53 (2) (2013)
Chih-Ting Yeh, Ming-Dou Ker
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. VLSI-DAT (2013)
Chih-Ting Yeh, Ming-Dou Ker
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. VLSI-DAT (2012)
Chih-Ting Yeh, Ming-Dou Ker
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications. Microelectron. Reliab. 52 (6) (2012)
Chih-Ting Yeh, Ming-Dou Ker
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs (3) (2012)
Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. ISCAS (2011)
Chih-Ting Yeh, Ming-Dou Ker
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. IEEE J. Solid State Circuits 45 (11) (2010)
Shih-Hung Chen, Chih-Ting Yeh
Active ESD protection design against cross-power-domain ESD stresses in CMOS integrated circuits. APCCAS (2008)