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New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process.
Chih-Ting Yeh
Ming-Dou Ker
Published in:
VLSI-DAT (2012)
Keyphrases
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power dissipation
power consumption
high speed
cmos technology
clock gating
chip design
power reduction
circuit design
real time
knowledge based systems
power electronics
nm technology
design process
user interface
information systems
artificial intelligence
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