New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology.
Chih-Ting YehMing-Dou KerPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2012)
Keyphrases
- cmos technology
- power dissipation
- low voltage
- power consumption
- low power
- silicon on insulator
- spl times
- clock gating
- high speed
- ibm power processor
- power reduction
- parallel processing
- power management
- mixed signal
- low cost
- image sensor
- design process
- digital signal processing
- user interface
- case study
- power system
- duty cycle
- single phase
- error resilience