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Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events.
Chih-Ting Yeh
Yung-Chih Liang
Ming-Dou Ker
Published in:
ISCAS (2011)
Keyphrases
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power consumption
power reduction
clock gating
steady state
case study
event detection
neural network
information systems
power system
temporal information
power dissipation
evolvable hardware
low voltage
electrical power
short circuit