Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process.
Chih-Ting YehMing-Dou KerPublished in: VLSI-DAT (2013)
Keyphrases
- high speed
- silicon on insulator
- semiconductor devices
- power consumption
- power reduction
- single phase
- clock gating
- cmos technology
- duty cycle
- electronic circuits
- chip design
- automatic detection
- circuit design
- analog circuits
- analog vlsi
- object detection
- power dissipation
- digital circuits
- false alarms
- frequency response
- steady state
- equivalent circuit
- low cost
- evolvable hardware
- field effect transistors
- low power
- detection rate
- false positives
- ibm power processor
- detection method