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An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS.

Chi-Wei LiuYi-Lun ChenPei-Chun LiaoShiau-Pin LinTing-Wei WangMing-Jie ChungPo-Hung ChenMing-Dou KerChung-Yu Wu
Published in: IEEE Trans. Circuits Syst. II Express Briefs (2019)
Keyphrases
  • high speed
  • cmos technology
  • data sets
  • neural network
  • computational complexity
  • image sequences
  • low cost
  • input data