ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup.

Ming-Dou Ker Che-Lun Hsu Wen-Yi Chen

Published in: ISCAS (2010)

Keyphrases

high voltage
high speed
circuit design
analog vlsi
steady state
vlsi circuits
low voltage
phase locked loop
partial discharge
operating conditions
normal operation
cmos technology
delay insensitive
low cost
power consumption
machine learning
artificial intelligence