Login / Signup
Po-Yen Chiu
Publication Activity (10 Years)
Years Active: 2007-2014
Publications (10 Years): 0
Top Topics
Cmos Technology
Design Considerations
Low Voltage
X Ray
Top Venues
IEEE Trans. Circuits Syst. I Regul. Pap.
Microelectron. Reliab.
SoCC
</>
Publications
</>
Po-Yen Chiu
,
Ming-Dou Ker
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit.
Microelectron. Reliab.
54 (1) (2014)
Po-Yen Chiu
,
Ming-Dou Ker
Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology.
SoCC
(2013)
Ming-Dou Ker
,
Po-Yen Chiu
Thin-Oxide Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
(10) (2013)
Ming-Dou Ker
,
Po-Yen Chiu
,
Fu-Yi Tsai
,
Yeong-Jar Chang
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.
ISCAS
(2009)
Yuan-Wen Hsiao
,
Ming-Dou Ker
,
Po-Yen Chiu
,
Chun Huang
,
Yuh-Kuang Tseng
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process.
SoCC
(2007)