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On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.
Ming-Dou Ker
Po-Yen Chiu
Fu-Yi Tsai
Yeong-Jar Chang
Published in:
ISCAS (2009)
Keyphrases
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low voltage
leakage current
cmos technology
design considerations
power consumption
power dissipation
low power
power line
power management
high speed
silicon on insulator
parallel processing
electrical properties
power reduction
image sequences
energy saving