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Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology.

Po-Yen ChiuMing-Dou Ker
Published in: SoCC (2013)
Keyphrases
  • cmos technology
  • logic circuits
  • low power
  • power dissipation
  • power consumption
  • design process
  • design considerations
  • case study
  • low voltage