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Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events.
Han-Sheng Huang
Ming-Dou Ker
Published in:
VLSI-DAT (2021)
Keyphrases
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power consumption
power dissipation
high speed
chip design
power reduction
circuit design
neural network
user interface
knowledge based systems
event detection
design decisions
single phase
duty cycle
database
power transmission
design principles
case study