Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology.
Federico A. AltolaguirreMing-Dou KerPublished in: ISCAS (2013)
Keyphrases
- cmos technology
- power consumption
- low voltage
- low power
- power dissipation
- silicon on insulator
- high speed
- spl times
- parallel processing
- leakage current
- image sensor
- power reduction
- power management
- low cost
- mixed signal
- pattern recognition
- clock frequency
- real time
- computer systems
- hardware and software
- energy saving
- random access memory