Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test.
Ming-Dou KerCheng-Cheng YenPublished in: IEEE J. Solid State Circuits (2008)
Keyphrases
- chip design
- high speed
- power dissipation
- circuit design
- built in self test
- ibm power processor
- design process
- power reduction
- power consumption
- functional verification
- user interface
- high level synthesis
- single chip
- experimental design
- cmos technology
- modular design
- physical design
- logic synthesis
- low power
- power system
- case study