• search
    search
  • reviewers
    reviewers
  • feeds
    feeds
  • assignments
    assignments
  • settings
  • logout

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process.

Yuan-Wen HsiaoMing-Dou Ker
Published in: Microelectron. Reliab. (2009)
Keyphrases
  • high speed
  • low power
  • input output
  • building blocks
  • computer aided
  • engineering design
  • real time
  • software architecture
  • design decisions