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Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection.

Seian-Feng LiaoKai-Neng TangMing-Dou KerJia-Rong YehHwa-Chyi ChiouYeh-Jen HuangChun-Chien TsaiYeh-Ning JouGeeng-Lih Lin
Published in: ECCTD (2015)
Keyphrases
  • high voltage
  • low voltage
  • design considerations
  • operating conditions
  • power line
  • partial discharge
  • response time
  • expert systems
  • power management
  • normal operation