Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology.
Federico A. AltolaguirreMing-Dou KerPublished in: VLSI-DAT (2013)
Keyphrases
- cmos technology
- low power
- high speed
- power consumption
- power dissipation
- silicon on insulator
- spl times
- low voltage
- power reduction
- digital signal processing
- mixed signal
- parallel processing
- low cost
- real time
- energy saving
- leakage current
- image sensor
- power management
- ibm power processor
- design methodology
- frame rate
- multi view
- flip flops