Chia-Hsiang Yang

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 67

Top Topics

Signal Processor

Ultrasound Imaging

Tensor Decomposition

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

VLSI Technology and Circuits

Publications

Tang Lee, Ting-Yang Chen, I-Hsuan Liu, Chia-Hsiang Yang
2.6 A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems. ISSCC (2024)
Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang
A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring. IEEE J. Solid State Circuits 59 (6) (2024)
Yi-Chen Chu, Yu-Cheng Lin, Yu-Chen Lo, Chia-Hsiang Yang
30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization. ISSCC (2024)
I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots. ISSCC (2023)
Sheng-Jung Yu, Yu-Chi Lee, Liang-Hsin Lin, Chia-Hsiang Yang
An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices. IEEE J. Solid State Circuits 58 (6) (2023)
Yen-Lung Chen, Chung-Hsuan Yang, Yi-Chung Wu, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing. ISSCC (2023)
Liang-Hsin Lin, Zih-Sing Fu, Po-Shao Chen, Bo-Yin Yang, Chia-Hsiang Yang
A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing. VLSI Technology and Circuits (2023)
Yi-Lin Lo, Yu-Chen Lo, Chia-Hsiang Yang
A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices. VLSI Technology and Circuits (2023)
Chung-Hsuan Yang, Yi-Chung Wu, Yen-Lung Chen, Chao-Hsi Lee, Jui-Hung Hung, Chia-Hsiang Yang
An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping. IEEE Trans. Biomed. Circuits Syst. 17 (6) (2023)
Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang
A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator. IEEE J. Solid State Circuits 58 (2) (2023)
Cheng-Yan Du, Chieh-Fu Tsai, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. ISSCC (2023)
Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun, Youngcheol Chae, Chia-Hsiang Yang
A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing. VLSI Technology and Circuits (2023)
Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang
A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for Seizure Prediction. IEEE J. Solid State Circuits 58 (1) (2023)
Tzu-Wei Tong, Yi-Yen Hsieh, Tai-Jung Chen, Chia-Hsiang Yang
A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition. A-SSCC (2023)
Chen-Chien Kao, Chiao-En Chen, Chia-Hsiang Yang
Hybrid Precoding Baseband Processor for 64 × 64 Millimeter Wave MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (4) (2022)
Zih-Sing Fu, Yu-Chi Lee, Alex Park, Chia-Hsiang Yang
A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training. VLSI Technology and Circuits (2022)
Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction. ISSCC (2022)
Chen-Chien Kao, Yi-Yen Hsieh, Chao-Hung Chen, Chia-Hsiang Yang
Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression. MWSCAS (2022)
Ying-Sheng Lin, Yi-Pao Wu, Yi-Chung Wu, Pei-Lin Lee, Chia-Hsiang Yang
Achieving Accurate Automatic Sleep Apnea/Hypopnea Syndrome Assessment Using Nasal Pressure Signal. IEEE J. Biomed. Health Informatics 26 (11) (2022)
Yu-Chen Lo, Yi-Chung Wu, Chia-Hsiang Yang
A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing. VLSI Technology and Circuits (2022)
Wen-Cong Huang, I-Ting Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality. VLSI Technology and Circuits (2022)
Chieh Chung, Chia-Hsiang Yang
A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots. IEEE J. Solid State Circuits 56 (1) (2021)
Yi-Lin Lo, Chia-Hsiang Yang
A Color Doppler Processing Engine with an Adaptive Clutter Filter for Portable Ultrasound Imaging Devices. ICASSP (2021)
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Li-Yang Tang, Yen-Fu Tu, Po-Chih Chang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification. IEEE J. Solid State Circuits 56 (10) (2021)
Sheng-Jung Yu, Yu-Chi Lee, Chia-Hsiang Yang
A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices. A-SSCC (2021)
Shuo-An Huang, Yi-Yen Hsieh, Chia-Hsiang Yang
Design optimization for ADMM-Based SVM Training Processor for Edge Computing. AICAS (2021)
Yen-Lung Chen, Bo-Yi Chang, Chia-Hsiang Yang, Tzi-Dar Chiueh
A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome. IEEE Trans. Parallel Distributed Syst. 32 (6) (2021)
Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang
4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images. ISSCC (2021)
Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Fu Zih-Sing, Chia-Hsiang Yang
A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring. A-SSCC (2021)
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. IEEE J. Solid State Circuits 56 (1) (2021)
Yung-Jen Lin, Yu-Chi Lee, Hao-Min Liu, Herming Chiueh, Tai-Shih Chi, Chia-Hsiang Yang
A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices With Speech Intelligibility Enhancement. IEEE Trans. Circuits Syst. (12) (2020)
Herming Chiueh, Chia-Hsiang Yang, Charles H.-P. Wen, Chao-Guang Yang, Po-Hao Chien, Ching-Yang Hung, Yu-Jui Chen, Yao-Pin Wang, Chin-Fong Chiu, Jer Lin
Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. VLSI-DAT (2020)
Chieh Chung, Chia-Hsiang Yang
21.2 A 1.5μJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots. ISSCC (2020)
Yao-Pin Wang, Chi-Chih Wen, Chen-Chien Kao, Chung-Jung Huang, Der-Zheng Liu, Chia-Hsiang Yang
Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax. GLOBECOM (2020)
Yi-Yen Hsieh, Yu-Chi Lee, Chia-Hsiang Yang
A CycleGAN Accelerator for Unsupervised Learning on Mobile Devices. ISCAS (2020)
Chi-Chih Wen, Yu-Chi Lee, Yi-Chung Wu, Chen-Chien Kao, Chia-Hsiang Yang
A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems. VLSI Circuits (2020)
Chia-Hsiang Yang
AI Acceleration with RISC-V for Edge Computing. VLSI-DAT (2020)
Shuo-An Huang, Kai-Chieh Chang, Horng-Huei Liou, Chia-Hsiang Yang
A 1.9-mW SVM Processor With On-Chip Active Learning for Epileptic Seizure Control. IEEE J. Solid State Circuits 55 (2) (2020)
Yu-Chi Lee, Tai-Shih Chi, Chia-Hsiang Yang
A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices. IEEE J. Solid State Circuits 55 (8) (2020)
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition. A-SSCC (2020)
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing. ISSCC (2020)
Shuo-An Huang, Chia-Hsiang Yang
A Hardware-Efficient ADMM-Based SVM Training Algorithm for Edge Computing. CoRR (2019)
Yu-Zhe Wang, Yao-Pin Wang, Yi-Chung Wu, Chia-Hsiang Yang
A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals. IEEE J. Solid State Circuits 54 (10) (2019)
Yan-Tong Chen, Wei-Cheng Sun, Chung-Chao Cheng, Tsung-Lin Tsai, Yeong-Luh Ueng, Chia-Hsiang Yang
An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Yu-Zhe Wang, Jingjie Wu, Shi-Hao Chen, Mango Chia-Tso Chao, Chia-Hsiang Yang
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. VLSI-DAT (2019)
Cheng-Hsun Lu, Yi-Chung Wu, Chia-Hsiang Yang
A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training. A-SSCC (2019)
Xin-Hong Qian, Yi-Chung Wu, Tzu-Yi Yang, Cheng-Hsiang Cheng, Hsing-Chien Chu, Wan-Hsueh Cheng, Ting-Yang Yen, Tzu-Han Lin, Yung-Jen Lin, Yu-Chi Lee, Jia-Heng Chang, Shih-Ting Lin, Shang-Hsuan Li, Tsung-Chen Wu, Chien-Chang Huang, Sung-Hao Wang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Tai-Shih Chi, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem. IEEE Trans. Biomed. Eng. 66 (11) (2019)
Wei-Cheng Sun, Yu-Chieh Su, Yeong-Luh Ueng, Chia-Hsiang Yang
An LDPC-Coded SCMA Receiver With Multi-User Iterative Detection and Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Wei-Cheng Sun, Yan-Tong Chen, Chia-Hsiang Yang, Yeong-Luh Ueng
Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems. IEEE Trans. Signal Process. 67 (6) (2019)
Yu-Chi Lee, Tai-Shih Chi, Chia-Hsiang Yang
A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices. AICAS (2019)
Chih-Hsuan Chiang, Shuo-An Huang, Chiao-En Chen, Chia-Hsiang Yang
A 2×2-16×16 Reconfigurable GGMD Processor for MIMO Communication Systems. ISCAS (2018)
Ting-I Chou, Kwuang-Han Chang, Jia-Yin Jhang, Shih-Wen Chiu, Guoxing Wang, Chia-Hsiang Yang, Herming Chiueh, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang
A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Chun-Yu Yeh, Ting-Chung Chu, Chiao-En Chen, Chia-Hsiang Yang
A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Tsung-Hsien Lin, Chia-Hsiang Yang, Seung-Tak Ryu
Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 53 (10) (2018)
Shuo-An Huang, Kai-Chieh Chang, Horng-Huei Liou, Chia-Hsiang Yang
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control. VLSI Circuits (2018)
Chia-Hsiang Yang
Massive MIMO detection VLSI design. VLSI-DAT (2018)
Yu-Zhe Wang, Yao-Pin Wang, Yi-Chung Wu, Chia-Hsiang Yang
A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. VLSI Circuits (2018)
Mao-Ruei Li, Chia-Hsiang Yang, Yeong-Luh Ueng
A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications. IEEE J. Solid State Circuits 52 (2) (2017)
Yi-Chung Wu, Jui-Hung Hung, Chia-Hsiang Yang
14.8 A 135mW fully integrated data processor for next-generation sequencing. ISSCC (2017)
Yi-Chung Wu, Chia-Hua Chang, Jui-Hung Hung, Chia-Hsiang Yang
A 135-mW Fully Integrated Data Processor for Next-Generation Sequencing. IEEE Trans. Biomed. Circuits Syst. 11 (6) (2017)
Yu-Cheng Tsai, Chiao-En Chen, Chia-Hsiang Yang
A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Wei-Cheng Sun, Chia-Hsiang Yang, Yen-Ming Chen, Yeong-Luh Ueng
An Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO Detectors. VTC Spring (2017)
Hsin-Tzu Lin, Yi-Chung Wu, Ping-Hsuan Hsieh, Chia-Hsiang Yang
Integration of energy-recycling logic and wireless power transfer for ultra-low-power implantables. ISCAS (2017)
Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, Shyh-Jye Jou
Error-resilient sequential cells with successive time borrowing for stochastic computing. ICASSP (2016)
Ting-I Chou, Shih-Wen Chiu, Kwuang-Han Chang, Yi-Ju Chen, Chen-Ting Tang, Chung-Hung Shih, Chih-Cheng Hsieh, Meng-Fan Chang, Chia-Hsiang Yang, Herming Chiueh, Kea-Tiong Tang
Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease. BioCAS (2016)
Cheng-Yen Lee, Ping-Hsuan Hsieh, Chia-Hsiang Yang
A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2016)
Chia-Hua Chang, Min-Te Chou, Yi-Chung Wu, Ting-Wei Hong, Yun-Lung Li, Chia-Hsiang Yang, Jui-Hung Hung
sBWT: memory efficient implementation of the hardware-acceleration-friendly Schindler transform for the fast biological sequence mapping. Bioinform. 32 (22) (2016)
Chia-Hsiang Yang, Chun-Wei Chou, Chia-Shen Hsu, Chiao-En Chen
A Systolic Array Based GTD Processor With a Parallel Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2015)
Wei-Cheng Sun, Wei-Hsuan Wu, Chia-Hsiang Yang, Yeong-Luh Ueng
An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Chiao-En Chen, Yu-Cheng Tsai, Chia-Hsiang Yang
An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems. IEEE Trans. Wirel. Commun. 14 (1) (2015)
Wei-Hsuan Wu, Wei-Cheng Sun, Chia-Hsiang Yang, Yeong-Luh Ueng
A 794Mbps 135mW iterative detection and decoding receiver for 4×4 LDPC-coded MIMO systems in 40nm. VLSIC (2015)
Chia-Hsiang Yang, Yi-Hsin Shih, Herming Chiueh
An 81.6 µW FastICA Processor for Epileptic Seizure Detection. IEEE Trans. Biomed. Circuits Syst. 9 (1) (2015)
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. IEEE J. Solid State Circuits 49 (1) (2014)
Chung-Chao Cheng, Jeng-Da Yang, Huang-Chang Lee, Chia-Hsiang Yang, Yeong-Luh Ueng
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Chia-Hsiang Yang, Ting-Ying Huang, Mao-Ruei Li, Yeong-Luh Ueng
A 5.4 µW Soft-Decision BCH Decoder for Wireless Body Area Networks. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Kea-Tiong Tang, Shih-Wen Chiu, Chung-Hung Shih, Chia-Ling Chang, Chia-Min Yang, Da-Jeng Yao, Jen-Huo Wang, Chien-Ming Huang, Hsin Chen, Kwuang-Han Chang, Chih-Cheng Hsieh, Ting-Hau Chang, Meng-Fan Chang, Chia-Min Wang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu
24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia. ISSCC (2014)
Shih-Wen Chiu, Jen-Huo Wang, Kwuang-Han Chang, Ting-Hau Chang, Chia-Min Wang, Chia-Lin Chang, Chen-Ting Tang, Chien-Fu Chen, Chung-Hung Shih, Han-Wen Kuo, Li-Chun Wang, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu, Kea-Tiong Tang
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia. IEEE Trans. Biomed. Circuits Syst. 8 (6) (2014)
Ching-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang, Shyh-Jye Jou
Power and area reduction in multi-stage addition using operand segmentation. VLSI-DAT (2013)
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Jin-Chern Chiou, Chih-Wei Chang, Lei-Chun Chou, Chung-Yu Wu
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control. ISSCC (2013)
Chiao-En Chen, Chia-Hsiang Yang
An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems. CoRR (2013)
Li-Lan Wang, Chia-Hsiang Yang, Herming Chiueh
A 191μW BPSK demodulator for data and power telemetry in biomedical implants. ACM Great Lakes Symposium on VLSI (2013)
Tsung-Han Yu, Chia-Hsiang Yang, Danijela Cabric, Dejan Markovic
A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios. IEEE J. Solid State Circuits 47 (9) (2012)
Yi-Hsin Shih, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh
Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection. APSIPA (2012)
Chia-Hsiang Yang, Tsung-Han Yu, Dejan Markovic
Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example. IEEE J. Solid State Circuits 47 (3) (2012)
Fang-Li Yuan, Chia-Hsiang Yang, Dejan Markovic
A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection. GLOBECOM (2011)
Tsung-Han Yu, Chia-Hsiang Yang, Dejan Markovic, Danijela Cabric
An Energy-Efficient VLSI Architecture for Cognitive Radio Wideband Spectrum Sensing. GLOBECOM (2011)
Chia-Hsiang Yang, Dejan Markovic
A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS. ESSCIRC (2009)
Chia-Hsiang Yang, Dejan Markovic
A Flexible DSP Architecture for MIMO Sphere Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2009)
Chia-Hsiang Yang, Dejan Markovic
A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels. ICC (2008)
Chia-Hsiang Yang, Dejan Markovic
A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications. GLOBECOM (2008)
Chia-Hsiang Yang, Yu-Hsuan Lin, Shih-Chun Lin, Tzi-Dar Chiueh
Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems. ISCAS (4) (2004)