Mango Chia-Tso Chao

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 14

Top Topics

Convolutional Neural Network

Outlier Detection

Pattern Generation

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao
Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods. VTS (2024)
Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu, Mango Chia-Tso Chao
Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information. ITC (2023)
Chin-Kuan Lin, Cheng-Che Lu, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao
Outlier Detection for Analog Tests Using Deep Learning Techniques. VTS (2023)
Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
CNN-Based Stochastic Regression for IDDQ Outlier Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Jhen-Gang Lin, Yu-Guang Chen, Yun-Wei Yang, Wei-Tse Hung, Cheng-Hong Tsai, De-Shiun Fu, Mango Chia-Tso Chao
DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network. ACM Great Lakes Symposium on VLSI (2023)
Wei-Tse Hung, Yu-Guang Chen, Jhen-Gang Lin, Yun-Wei Yang, Cheng-Hong Tsai, Mango Chia-Tso Chao
DRC Violation Prediction After Global Route Through Convolutional Neural Network. IEEE Trans. Very Large Scale Integr. Syst. 31 (9) (2023)
Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS (2021)
Wei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, Mango Chia-Tso Chao
Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network. ISPD (2020)
Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS (2020)
Yu-Zhe Wang, Jingjie Wu, Shi-Hao Chen, Mango Chia-Tso Chao, Chia-Hsiang Yang
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. VLSI-DAT (2019)
Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC (2019)
Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao
Fast WAT test structure for measuring Vt variance based on latch-based comparators. VTS (2017)
Wen-Hsiang Chang, Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu, Mango Chia-Tso Chao, Cheng-Hong Tsai, Yen-Chih Chiu
Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique. ISPD (2016)
Harry H. Chen, Shih-Hua Kuo, Jonathan Tung, Mango Chia-Tso Chao
Statistical techniques for predicting system-level failure using stress-test data. VTS (2015)
Hao-Yu Yang, Rei-Fu Huang, Chin-Lung Su, Kuan-Hong Lin, Hang-Kaung Shu, Chi-Wei Peng, Mango Chia-Tso Chao
Testing methods for quaternary content addressable memory using charge-sharing sensing scheme. ITC (2015)
Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Chris Lin, Mango Chia-Tso Chao
Random pattern generation for post-silicon validation of DDR3 SDRAM. VTS (2015)
Tseng-Chin Luo, Mango Chia-Tso Chao, Huan-Chi Tseng, Masaharu Goto, Philip A. Fisher, Yuan-Yao Chang, Chi-Min Chang, Takayuki Takao, Katsuhito Iwasaki, Cheng Mao Lee
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization. IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Chen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu
Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Yi-Ming Wang, Mango Chia-Tso Chao, Shi-Hao Chen, Hung-Chun Li
Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs. VLSI-DAT (2014)
Wen-Hsiang Chang, Mango Chia-Tso Chao, Shi-Hao Chen
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer. IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Hao-Yu Yang, Chen-Wei Lin, Chao-Ying Huang, Ching-Ho Lu, Chen-An Lai, Mango Chia-Tso Chao, Rei-Fu Huang
Testing methods for a write-assist disturbance-free dual-port SRAM. VTS (2014)
Chen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu
Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs. VTS (2013)
Chen-Wei Lin, Chin-Yuan Huang, Mango Chia-Tso Chao
Testing of a low-VMIN data-aware dynamic-supply 8T SRAM. VTS (2013)
Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Chin-Yuan Huang, Mango Chia-Tso Chao, Rei-Fu Huang
Fault Models and Test Methods for Subthreshold SRAMs. IEEE Trans. Computers 62 (3) (2013)
Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Mango Chia-Tso Chao
Testing retention flip-flops in power-gated designs. VTS (2013)
Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao
Power-Up Sequence Control for MTCMOS Designs. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
Testing strategies for a 9T sub-threshold SRAM. ITC (2012)
Yi-Ming Wang, Shi-Hao Chen, Mango Chia-Tso Chao
An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs. ASP-DAC (2012)
Rei-Fu Huang, Hao-Yu Yang, Mango Chia-Tso Chao, Shih-Chin Lin
Alternate hammering test for application-specific DRAMs and an industrial case study. DAC (2012)
Hao-Yu Yang, Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Shih-Chin Lin
Testing Methodology of Embedded DRAMs. IEEE Trans. Very Large Scale Integr. Syst. 20 (9) (2012)
Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen
Design-for-debug layout adjustment for FIB probing and circuit editing. ITC (2011)
Chen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, Mango Chia-Tso Chao
Detecting stability faults in sub-threshold SRAMs. ICCAD (2011)
Mango Chia-Tso Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang
A Novel Test Flow for One-Time-Programming Applications of NROM Technology. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Tseng-Chin Luo, Eric Leong, Mango Chia-Tso Chao, Philip A. Fisher, Wen-Hsiang Chang
Mask versus Schematic - an enhanced design-verification flow for first silicon success. ITC (2010)
Yu-Ze Wu, Mango Chia-Tso Chao
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes. ACM Trans. Design Autom. Electr. Syst. 16 (1) (2010)
Szu-Pang Mu, Mango Chia-Tso Chao
Theoretical analysis for low-power test decompression using test-slice duplication. VTS (2010)
Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. ICCAD (2010)
Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang
Fault models and test methods for subthreshold SRAMs. ITC (2010)
Mango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin
Mathematical yield estimation for two-dimensional-redundancy memory arrays. ICCAD (2010)
Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang
A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang
A metal-only-ECO solver for input-slew and output-loading violations. ISPD (2009)
Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu
Multiple-Fault Diagnosis Using Faulty-Region Identification. VTS (2009)
Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango Chia-Tso Chao
A novel test flow for one-time-programming applications of NROM technology. ITC (2009)
Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin
Fault models for embedded-DRAM macros. DAC (2009)
Tseng-Chin Luo, Mango Chia-Tso Chao, Michael S.-Y. Wu, Kuo-Tsai Li, Chin C. Hsia, Huan-Chi Tseng, Chuen-Uan Huang, Yuan-Yao Chang, Samuel C. Pan, Konrad K.-L. Young
A novel array-based test methodology for local process variation monitoring. ITC (2009)
Tsun-Ming Tseng, Mango Chia-Tso Chao, Chien Pang Lu, Chen Hsing Lo
Power-switch routing for coarse-grain MTCMOS technologies. ICCAD (2009)
Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen
Testing Methodology of Embedded DRAMs. ITC (2008)
Yu-Ze Wu, Mango Chia-Tso Chao
Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes. VTS (2008)
Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei
A hybrid scheme for compacting test responses with unknown values. ICCAD (2007)
Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng
Coverage loss by using space compactors in presence of unknown values. DATE (2006)
Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. DAC (2006)
Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
Response shaper: a novel technique to enhance unknown tolerance for output response compaction. ICCAD (2005)
Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. ICCD (2005)
Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
Pattern Selection for Testing of Deep Sub-Micron Timing Defects. DATE (2004)
Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang
A clustering- and probability-based approach for time-multiplexed FPGA partitioning. Integr. 38 (2) (2004)
Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. ICCD (2001)
Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang
A clustering- and probability-based approach for time-multiplexed FPGA partitioning. ICCAD (1999)