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Jai-Ming Lin
ORCID
Publication Activity (10 Years)
Years Active: 1998-2024
Publications (10 Years): 27
Top Topics
Fixed Number
Optimization Algorithm
Analytical Models
Scales Linearly
Top Venues
ICCAD
IEEE Trans. Very Large Scale Integr. Syst.
ISPD
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
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Publications
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Jai-Ming Lin
,
You-Yu Chang
,
Wei-Lun Huang
Timing-Driven Analytical Placement According to Expected Cell Distribution Range.
ISPD
(2024)
Jai-Ming Lin
,
Yu-Chien Lin
,
Hsuan Kung
,
Wei-Yuan Lin
HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique.
ICCAD
(2023)
Jai-Ming Lin
,
Yu-Tien Chen
,
Yang-Tai Kung
,
Hao-Jia Lin
Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network.
ISPD
(2023)
Jai-Ming Lin
,
Tsung-Chun Tsai
,
Rui-Ting Shen
Routability-Driven Orientation-Aware Analytical Placement for System in Package.
ICCAD
(2023)
Jai-Ming Lin
,
Tsung-Lin Tsai
,
Tsung-Chun Tsai
Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package.
IEEE Trans. Very Large Scale Integr. Syst.
31 (9) (2023)
Jai-Ming Lin
,
Hao-Yuan Hsieh
,
Hsuan Kung
,
Hao-Jia Lin
Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs.
ICCAD
(2022)
Jai-Ming Lin
,
Po-Chen Lu
,
Heng-Yu Lin
,
Jia-Ting Tsai
A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS.
ICCAD
(2022)
Jai-Ming Lin
,
Liang-Chi Zane
,
Min-Chia Tsai
,
Yung-Chen Chen
,
Che-Li Lin
,
Chen-Fa Tsai
PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability.
IEEE Trans. Very Large Scale Integr. Syst.
30 (11) (2022)
Jai-Ming Lin
,
Wei-Yi Chang
,
Hao-Yuan Hsieh
,
Ya-Ting Shyu
,
Yeong-Jar Chang
,
Juin-Ming Lu
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.
IEEE Trans. Very Large Scale Integr. Syst.
29 (9) (2021)
Jai-Ming Lin
,
Yang-Tai Kung
,
Zheng-Yu Huang
,
I-Ru Chen
A Fast Power Network Optimization Algorithm for Improving Dynamic IR-drop.
ISPD
(2021)
Jai-Ming Lin
,
You-Lun Deng
,
Ya-Chu Yang
,
Jia-Jian Chen
,
Po-Chen Lu
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs.
IEEE Trans. Very Large Scale Integr. Syst.
29 (5) (2021)
Jai-Ming Lin
,
Wei-Fan Huang
,
Yao-Chieh Chen
,
Yi-Ting Wang
,
Po-Wen Wang
DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs.
ICCAD
(2021)
Jai-Ming Lin
,
Chung-Wei Huang
,
Liang-Chi Zane
,
Min-Chia Tsai
,
Che-Li Lin
,
Chen-Fa Tsai
Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs.
ICCAD
(2021)
Jai-Ming Lin
,
Tai-Ting Chen
,
Hao-Yuan Hsieh
,
Ya-Ting Shyu
,
Yeong-Jar Chang
,
Juin-Ming Lu
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation.
IEEE Trans. Very Large Scale Integr. Syst.
29 (5) (2021)
Jai-Ming Lin
,
Szu-Ting Li
,
Yi-Ting Wang
Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros.
DAC
(2019)
Jai-Ming Lin
,
You-Lun Deng
,
Ya-Chu Yang
,
Jia-Jian Chen
,
Yao-Chieh Chen
A Novel Macro Placement Approach based on Simulated Evolution Algorithm.
ICCAD
(2019)
Jai-Ming Lin
,
You-Lun Deng
,
Szu-Ting Li
,
Bo-Heng Yu
,
Li-Yen Chang
,
Te-Wei Peng
Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles.
IEEE Trans. Very Large Scale Integr. Syst.
27 (1) (2019)
Jai-Ming Lin
,
Chien-Yu Huang
,
Jhih-Ying Yang
Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs.
DATE
(2018)
Jai-Ming Lin
,
Tai-Ting Chen
,
Yen-Fu Chang
,
Wei-Yi Chang
,
Ya-Ting Shyu
,
Yeong-Jar Chang
,
Juin-Ming Lu
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.
ICCAD
(2018)
Jai-Ming Lin
,
Chien-Yu Huang
General floorplanning methodology for 3D ICs with an arbitrary bonding style.
DATE
(2018)
Jai-Ming Lin
,
Jhih-Sheng Syu
,
I-Ru Chen
Macro-aware row-style power delivery network design for better routability.
ICCAD
(2018)
Jai-Ming Lin
,
Bo-Heng Yu
,
Li-Yen Chang
Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits.
ASP-DAC
(2017)
Jai-Ming Lin
,
Jung-An Yang
Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
36 (11) (2017)
Chun-Po Huang
,
Jai-Ming Lin
,
Ya-Ting Shyu
,
Soon-Jyh Chang
A Systematic Design Methodology of Asynchronous SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst.
24 (5) (2016)
Ya-Ting Shyu
,
Jai-Ming Lin
,
Che-Chun Lin
,
Chun-Po Huang
,
Soon-Jyh Chang
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
35 (10) (2016)
Liang-Ying Lu
,
Ching-Yao Chang
,
Zhao-Hong Chen
,
Bo-Ting Yeh
,
Tai-Hua Lu
,
Peng-Yu Chen
,
Pin-Hao Tang
,
Kuen-Jong Lee
,
Lih-Yih Chiou
,
Soon-Jyh Chang
,
Chien-Hung Tsai
,
Chung-Ho Chen
,
Jai-Ming Lin
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.
ASP-DAC
(2016)
Jai-Ming Lin
,
Po-Yang Chiu
,
Yen-Fu Chang
SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs.
ICCAD
(2016)
Jai-Ming Lin
,
Che-Chun Lin
Placement Density Aware Power Switch Planning Methodology for Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
34 (5) (2015)
Jai-Ming Lin
,
Chih-Yao Hu
,
Kai-Chung Chan
Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint.
VLSI-DAT
(2015)
Jai-Ming Lin
,
Ji-Heng Wu
F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
33 (11) (2014)
Jai-Ming Lin
,
Che-Chun Lin
,
Zong-Wei Syu
,
Chih-Chung Tsai
,
Kevin Huang
Current density aware power switch placement algorithm for power gating designs.
ISPD
(2014)
Ya-Ting Shyu
,
Jai-Ming Lin
,
Chun-Po Huang
,
Cheng-Wu Lin
,
Ying-Zu Lin
,
Soon-Jyh Chang
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
21 (4) (2013)
Jai-Ming Lin
,
Zhi-Xiong Hung
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems.
IEEE Trans. Very Large Scale Integr. Syst.
20 (3) (2012)
Cheng-Wu Lin
,
Chung-Lin Lee
,
Jai-Ming Lin
,
Soon-Jyh Chang
Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits.
ICCAD
(2012)
Jai-Ming Lin
,
Wei-Yi Cheng
,
Chung-Lin Lee
,
Richard C. Hsu
Voltage island-driven floorplanning considering level shifter placement.
ASP-DAC
(2012)
Cheng-Wu Lin
,
Jai-Ming Lin
,
Yen-Chih Chiu
,
Chun-Po Huang
,
Soon-Jyh Chang
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
31 (12) (2012)
Cheng-Wu Lin
,
Cheng-Chung Lu
,
Jai-Ming Lin
,
Soon-Jyh Chang
Routability-driven placement algorithm for analog integrated circuits.
ISPD
(2012)
Jia-Ru Chuang
,
Jai-Ming Lin
Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction.
ASP-DAC
(2011)
Cheng-Wu Lin
,
Jai-Ming Lin
,
Yen-Chih Chiu
,
Chun-Po Huang
,
Soon-Jyh Chang
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.
DAC
(2011)
Jai-Ming Lin
,
Zhi-Xiong Hung
UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
30 (7) (2011)
Cheng-Wu Lin
,
Jai-Ming Lin
,
Chun-Po Huang
,
Soon-Jyh Chang
Performance-driven analog placement considering boundary constraint.
DAC
(2010)
Jai-Ming Lin
,
Hsi Hung
UFO: unified convex optimization algorithms for fixed-outline floorplanning.
ASP-DAC
(2010)
Jai-Ming Lin
,
Guang-Ming Wu
,
Yao-Wen Chang
,
Jen-Hui Chuang
Placement with symmetry constraints for analog layout design using TCG-S.
ASP-DAC
(2005)
Jai-Ming Lin
,
Yao-Wen Chang
TCG: A transitive closure graph-based representation for general floorplans.
IEEE Trans. Very Large Scale Integr. Syst.
13 (2) (2005)
Jai-Ming Lin
,
Yao-Wen Chang
-admissible representations for general floorplans.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
23 (6) (2004)
Jai-Ming Lin
,
Song-Ra Pan
,
Yao-Wen Chang
Graph matching-based algorithms for array-based FPGA segmentation design and routing.
ASP-DAC
(2003)
Jai-Ming Lin
,
Yao-Wen Chang
,
Shih-Ping Lin
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.
IEEE Trans. Very Large Scale Integr. Syst.
11 (4) (2003)
Jai-Ming Lin
,
Hsin-Lung Chen
,
Yao-Wen Chang
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.
IEEE Trans. Very Large Scale Integr. Syst.
10 (6) (2002)
Jai-Ming Lin
,
Hsin-Lung Chen
,
Yao-Wen Chang
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.
DATE
(2002)
Guang-Ming Wu
,
Jai-Ming Lin
,
Yao-Wen Chang
Performance-driven placement for dynamically reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst.
7 (4) (2002)
Jai-Ming Lin
,
Yao-Wen Chang
-admissible representations for general floorplans.
DAC
(2002)
Jai-Ming Lin
,
Yao-Wen Chang
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.
DAC
(2001)
Yao-Wen Chang
,
Jai-Ming Lin
,
Martin D. F. Wong
Matching-based algorithm for FPGA channel segmentation design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
20 (6) (2001)
Guang-Ming Wu
,
Jai-Ming Lin
,
Yao-Wen Chang
Generic ILP-based approaches for time-multiplexed FPGA partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
20 (10) (2001)
Guang-Ming Wu
,
Jai-Ming Lin
,
Mango Chia-Tso Chao
,
Yao-Wen Chang
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.
ICCD
(2001)
Guang-Ming Wu
,
Jai-Ming Lin
,
Yao-Wen Chang
An Algorithm for Dynamically Reconfigurable FPGA Placement.
ICCD
(2001)
Yao-Wen Chang
,
Jai-Ming Lin
,
D. F. Wong
Graph matching-based algorithms for FPGA segmentation design.
ICCAD
(1998)