Chung-Ho Chen

Publication Activity (10 Years)

Years Active: 1982-2024
Publications (10 Years): 12

Top Topics

Execution Model

Top Venues

Publications

Ta-Chun Lo, Shan-Hong Yang, Jyh-Biau Chang, Chung-Ho Chen, Ce-Kuen Shieh
A Two-Phase Multi-Class Botnet Labeling Approach for Real-World Traffic. ICAIIC (2024)
Tsung-Han Tsou, Dun-Jie Chen, Sheng-Yang Hung, Yu-Hsiang Wang, Chung-Ho Chen
Optimization of Stride Prefetching Mechanism and Dependent Warp Scheduling on GPGPU. ISCAS (2020)
Yu-Xiang Su, Jhi-Han Jheng, Dun-Jie Chen, Chung-Ho Chen
Development of an Open ISA GPGPU for Edge Device Machine Learning Applications. ICUFN (2019)
Min-Zhi Ji, Wei-Chung Tseng, Ting-Jia Wu, Bo-Rong Lin, Chung-Ho Chen
Micro Darknet For Inference: ESL reference for inference accelerator design. ISOCC (2019)
Chung-Ho Chen
A glance of the CASLab HSAIL SIMT GPU for OpenCL and TensorFlow applications. VLSI-DAT (2018)
Kuan-Chung Chen, Chung-Ho Chen
Enabling SIMT Execution Model on Homogeneous Multi-Core System. ACM Trans. Archit. Code Optim. 15 (1) (2018)
Sen-Chih Tsai, Yu-Xiang Su, Yu-Han Chin, Wei-Zhong Ceng, Chung-Ho Chen
Kernel Aware Warp Scheduler. ISCAS (2018)
Ching-Wen Lin, Chung-Ho Chen
Processor shield for L1 data cache software-based on-line self-testing. ASP-DAC (2017)
Ching-Wen Lin, Chung-Ho Chen
A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform. IEEE Trans. Very Large Scale Integr. Syst. 25 (8) (2017)
Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu, Chung-Ho Chen
Dynamic SIMD re-convergence with paired-path comparison. ISCAS (2016)
Ching-Wen Lin, Chung-Ho Chen
A processor shield for software-based on-line self-test. APCCAS (2016)
Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. ASP-DAC (2016)
Chien-Hsuan Yen, Chung-Ho Chen, Kuan-Chung Chen
A memory-efficient NoC system for OpenCL many-core platform. ISCAS (2015)
Ching-Wen Lin, Chung-Ho Chen
Unambiguous I-cache testing using software-based self-testing methodology. ISCAS (2014)
En-Hao Chang, Chen-Chieh Wang, Chien-Te Liu, Kuan-Chung Chen, Chung-Ho Chen
Virtualization Technology for TCP/IP Offload Engine. IEEE Trans. Cloud Comput. 2 (2) (2014)
Kuan-Chung Chen, Chung-Ho Chen
An OpenCL runtime system for a heterogeneous many-core virtual platform. ISCAS (2014)
Chien-Te Liu, Kuan-Chung Chen, Chung-Ho Chen
CASL hypervisor and its virtualization platform. ISCAS (2013)
Tzu-Hsuan Hsu, Ching-Wen Lin, Chung-Ho Chen
Using condition flag prediction to improve the performance of out-of-order processors. ISCAS (2013)
Chen-Chieh Wang, Chung-Ho Chen
A System-Level Network Virtual Platform for IPsec Processor Development. IEICE Trans. Inf. Syst. (5) (2013)
Hsu-Yao Huang, Chi-Yuan Huang, Chung-Ho Chen
Tile-based GPU optimizations through ESL full system simulation. ISCAS (2012)
Eric Shianda Yu, Chung-Ho Chen
A SIMD-accelerated software rendering pipeline for 3D graphics processing. APCCAS (2012)
Chen-Chieh Wang, Sheng-Hsin Lo, Yao-Ning Liu, Chung-Ho Chen
NetVP: A system-level NETwork Virtual Platform for network accelerator development. ISCAS (2012)
Yi-Ying Tsai, Chung-Ho Chen
Energy-Efficient Trace Reuse Cache for Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 19 (9) (2011)
Chung-Ho Chen, Chih-Lun Lu
Optimum profit model based on order quantity, product price, and process quality level. Expert Syst. Appl. 38 (6) (2011)
Chung-Ho Chen, Chih-Lun Lu
Optimum profit model considering production, quality and sale problem. Int. J. Syst. Sci. 42 (12) (2011)
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. IEEE Trans. Very Large Scale Integr. Syst. 19 (3) (2011)
Yi-Li Lin, Wei-Tso Chen, Alvin W. Y. Su, Da-Wei Chang, Chung-Ho Chen
A low cost, low power, high scalability and dependability processor-cluster platform. SIES (2011)
Shye-Tzeng Shen, Shin-Ying Lee, Chung-Ho Chen
Full system simulation with QEMU: An approach to multi-view 3D GPU design. ISCAS (2010)
Chung-Ho Chen, Wan-Lin Chang
Optimal design of expected lifetime and warranty period for product with quality loss and inspection error. Expert Syst. Appl. 37 (4) (2010)
Michael Boon Chong Khoo, Zhang Wu, Chung-Ho Chen, Kah Wai Yeong
Using one EWMA chart to jointly monitor the process mean and variance. Comput. Stat. 25 (2) (2010)
Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao
Full System Simulation and Verification Framework. IAS (2009)
Chung-Ho Chen, Michael B. C. Khoo
Optimum process mean and manufacturing quantity settings for serial production system under the quality loss and rectifying inspection plan. Comput. Ind. Eng. 57 (3) (2009)
Chung-Ho Chen, Hui-Sung Kao
The determination of optimum process mean and screening limits based on quality loss function. Expert Syst. Appl. 36 (3) (2009)
Wei-Cheng Lin, Chung-Ho Chen
Avoiding unnecessary frame memory access and multi-frame motion estimation computation in H.264/AVC. ISCAS (2008)
Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen
A Software-Based Test Methodology for Direct-Mapped Data Cache. ATS (2008)
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
A hybrid software-based self-testing methodology for embedded processor. SAC (2008)
Chung-Ming Chen, Chung-Ho Chen
Configurable VLSI Architecture for Deblocking Filter in H.264/AVC. IEEE Trans. Very Large Scale Integr. Syst. 16 (8) (2008)
Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen
Address compression for scalable load/store queue implementation. ISCAS (2008)
Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen
Power-efficient and scalable load/store queue design via address compression. SAC (2008)
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
A hybrid self-testing methodology of processor cores. ISCAS (2008)
Chung-Ho Chen
Economic Production Run Length and warranty Period for Product with Weibull Lifetime. Asia Pac. J. Oper. Res. 25 (6) (2008)
Wei-Cheng Lin, Chung-Ho Chen
Frame Buffer Access Reduction for MPEG Video Decoder. IEEE Trans. Circuits Syst. Video Technol. 18 (10) (2008)
Chung-Ho Chen, Min-Tsai Lai
Economic manufacturing quantity, optimum process mean, and economic specification limits setting under the rectifying inspection plan. Eur. J. Oper. Res. 183 (1) (2007)
Wei-Cheng Lin, Chung-Ho Chen
A data-reuse scheme for avoiding unnecessary memory accesses in MPEG-4 ASP video decoder. SoCC (2007)
Chung-Ho Chen, Kuo-Su Hsiao
Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality. IEEE Trans. Computers 56 (11) (2007)
Chung-Ming Chen, Chung-Ho Chen
An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC. IEICE Trans. Inf. Syst. (1) (2007)
Chung-Ho Chen, Min-Tsai Lai
Determining the optimum process mean based on quadratic quality loss function and rectifying inspection plan. Eur. J. Oper. Res. 182 (2) (2007)
Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao
Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores. IEEE Trans. Very Large Scale Integr. Syst. 15 (5) (2007)
Wei-Cheng Lin, Chung-Ho Chen
Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG Video Encoder. ICCCN (2007)
Kuo-Su Hsiao, Chung-Ho Chen
Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation. IEEE Trans. Very Large Scale Integr. Syst. 14 (10) (2006)
Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, Han-Chiang Chen
Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator. LCN (2006)
Chao-Yu Chou, Yu-Chang Lin, Chun-Lang Chang, Chung-Ho Chen
. Reliab. Eng. Syst. Saf. 91 (4) (2006)
Kuo-Su Hsiao, Chung-Ho Chen
Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling. ICCD (2006)
Chao-Yu Chou, Chun-Hua Chen, Chung-Ho Chen
control charts using genetic algorithms. Expert Syst. Appl. 30 (2) (2006)
Wei-Cheng Lin, Chung-Ho Chen
Exploring reusable frame buffer data for MPEG-4 video decoding. ISCAS (2006)
Chung-Ming Chen, Chung-Ho Chen
An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding. Computer Graphics and Imaging (2005)
Chung-Ming Chen, Chung-Ho Chen
An efficient VLSI architecture for edge filtering in H.264/AVC. Circuits, Signals, and Systems (2005)
Kuo-Su Hsiao, Chung-Ho Chen
An efficient wakeup design for energy reduction in high-performance superscalar processors. Conf. Computing Frontiers (2005)
Ning-Yaun Ker, Chung-Ho Chen
An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems. ASP-DAC (2003)
Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen
Parameterized MAC unit implementation. ASP-DAC (2001)
Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo
A Systematic Approach for Parallel CRC Computations. J. Inf. Sci. Eng. 17 (3) (2001)
Chung-Ho Chen, Feng-Fu Lin
An Easy-to-Use Approach for Practical Bus-Based System Design. IEEE Trans. Computers 48 (8) (1999)
Chung-Ho Chen, Arun K. Somani
Fault Containment in Cache Memories for TMR Redundant Processor Systems. IEEE Trans. Computers 48 (4) (1999)
Chung-Ho Chen, Akida Wu
An enhanced DLX-based superscalar system simulator. WCAE@HPCA (1997)
Chung-Ho Chen, Akida Wu
Microarchitecture Support for Improving the Performance of Load Target Prediction. MICRO (1997)
Craig M. Wittenbrink, Arun K. Somani, Chung-Ho Chen
Cache write generate for parallel image processing on shared memory architectures. IEEE Trans. Image Process. 5 (7) (1996)
Chung-Ho Chen, Arun K. Somani
Architecture Technique Trade-Offs Using Mean Memory Delay Time. IEEE Trans. Computers 45 (10) (1996)
Robert M. Haralick, Arun K. Somani, Craig M. Wittenbrink, Robert Johnson, Kenneth Cooper, Linda G. Shapiro, Ihsin T. Phillips, Jenq-Neng Hwang, William Cheung, Yung Hsi Yao, Chung-Ho Chen, Larry Yang, Brian Daugherty, Bob Lorbeski, Kent Loving, Tom Miller, Larye Parkins, Steve Soos
Proteus: A reconfigurable computational network for computer vision. Mach. Vis. Appl. 8 (2) (1995)
Chung-Ho Chen, Arun K. Somani
A Unified Architectural Tradeoff Methodology. ISCA (1994)
Chung-Ho Chen, Arun K. Somani
A Cache Protocol for Error Detection and Recovery in Fault-Tolerant Computing Systems. FTCS (1994)
Chung-Ho Chen, Arun K. Somani
Effects of Cache Traffic on Shared Bus Multiprocessor Systems. ICPP (1) (1992)
Robert M. Haralick, Arun K. Somani, Craig M. Wittenbrink, Robert Johnson, Kenneth Cooper, Linda G. Shapiro, Ihsin T. Phillips, Jenq-Neng Hwang, William Cheung, Yung Hsi Yao, Chung-Ho Chen, Larry Yang, Brian Daugherty, Bob Lorbeski, Kent Loving, Tom Miller, Larye Parkins, Steve Soos
Proteus: a reconfigurable computational network for computer vision. ICPR (4) (1992)
Arun K. Somani, Craig M. Wittenbrink, Robert M. Haralick, Linda G. Shapiro, Jenq-Neng Hwang, Chung-Ho Chen, Robert Johnson, Kenneth Cooper
Proteus System Architecture and Organization. IPPS (1991)
Chung-Ho Chen
An Algebraic Model of Arithmetic Codes. IEEE Trans. Computers 31 (4) (1982)