Lih-Yih Chiou

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 21

Top Topics

Air Conditioning

Top Venues

IET Comput. Digit. Tech.

Publications

Lih-Yih Chiou, Hong-Ming Shih, Shun-Hsiu Hsu, Zu-Cheng Sheng, Soon-Jyh Chang
Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator. ISCAS (2024)
Chi-Ray Huang, Lih-Yih Chiou
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM. IEEE Trans. Very Large Scale Integr. Syst. 29 (8) (2021)
Lih-Yih Chiou, Jing-Yu Huang, Chi-Kuan Li, Chen-Chung Tsai
A Reliable Near-Threshold Voltage SRAM-Based PUF Utilizing Weight Detection Technique. VLSI-DAT (2021)
Lih-Yih Chiou, Tsung-Han Yang, Jian-Tang Syu, Che-Pin Chang, Yeong-Jar Chang
Intelligent Policy Selection for GPU Warp Scheduler. AICAS (2019)
Lih-Yih Chiou, Chao-Kai Yang, Che-Pin Chang
A Data-Traffic Aware Dynamic Power Management for General-Purpose Graphics Processing Units. ISCAS (2019)
Lih-Yih Chiou, Chung-Han Wu, Po-Cheng Wei
A Reliable Delay-Based Physical Unclonable Function with Dark-Bit Avoidance. ISCAS (2019)
Lih-Yih Chiou, Chi-Ray Huang, Chang-Chieh Cheng, Jing-Yu Huang, Wei-Suo Ling
A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs. VLSI-DAT (2019)
Chi-Ray Huang, Lih-Yih Chiou
Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation. IET Circuits Devices Syst. 12 (6) (2018)
Tsai-Kan Chien, Lih-Yih Chiou, Chi-Shian Chang, Jing-Yu Huang, Chung-Han Wu, Heng-Yuan Lee, Shyh-Shyuan Sheu
/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM. IEEE Trans. Circuits Syst. II Express Briefs (9) (2018)
Liang-Ying Lu, Lih-Yih Chiou
Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (12) (2018)
Liang-Ying Lu, Tsung-Yu Hsieh, Pei-En Weng, Lih-Yih Chiou
Methodology for developing virtual platforms from power-aware to power- and thermal-aware at electronic system level. IET Cyper-Phys. Syst.: Theory & Appl. 3 (3) (2018)
Lih-Yih Chiou, Chun-Hao Chang, Liang-Ying Lu, Wei-Hsuan Yang, Yeong-Jar Chang, Juin-Ming Lu
Fast Steady-State Thermal Analysis. ISOCC (2018)
Chi-Ray Huang, Kuan-Lin Wu, Chung-Han Wu, Lih-Yih Chiou
Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme. ISCAS (2018)
Tsai-Kan Chien, Lih-Yih Chiou, Yi-Sung Tsou, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu
Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches. ISLPED (2017)
Liang-Ying Lu, Lih-Yih Chiou
Temperature gradient-aware thermal simulator for three-dimensional integrated circuits. IET Comput. Digit. Tech. 11 (5) (2017)
Hugo Cruz, Hong-Yi Huang, Ching-Hsing Luo, Lih-Yih Chiou, Shuenn-Yuh Lee
A novel clock-pulse-width calibration technique for charge redistribution DACs. ISCAS (2017)
Tsai-Kan Chien, Lih-Yih Chiou, Chieh-Wen Cheng, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu
Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture. APCCAS (2016)
Tsai-Kan Chien, Lih-Yih Chiou, Yao-Chun Chuang, Shyh-Shyuan Sheu, Heng-Yuan Li, Pei-Hua Wang, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu
A low store energy and robust ReRAM-based flip-flop for normally off microprocessors. ISCAS (2016)
Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. ASP-DAC (2016)
Tsai-Kan Chien, Lih-Yih Chiou, Shyh-Shyuan Sheu, Jing-Cian Lin, Chang-Chia Lee, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu
Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (2) (2016)
Lih-Yih Chiou, Liang-Ying Lu, Chieh-Yu Lin
An effective matrix compression method for GPU-accelerated thermal analysis. VLSI-DAT (2015)
Lih-Yih Chiou, Chi-Ray Huang, Ming-Hung Wu
A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits. ISCAS (2014)
Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou
An ultra-low-power adaptive-body-bias control for subthreshold circuits. VLSI-DAT (2014)
Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion. ISCAS (2012)
Lih-Yih Chiou, Liang-Ying Lu, Bo-Chi Lin, Alan P. Su
Buffer size minimization method considering mix-clock domains and discontinuous data access. APCCAS (2012)
Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang
A fast and effective dynamic trace-based method for analyzing architectural performance. ASP-DAC (2011)
Shien-Chun Luo, Lih-Yih Chiou
A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing. IEEE Trans. Circuits Syst. II Express Briefs (6) (2010)
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. J. Signal Process. Syst. 58 (2) (2010)
Lih-Yih Chiou, Yi-Siou Chen, Chih-Hsien Lee
System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (8) (2009)
Lih-Yih Chiou, Shien-Chun Luo
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics. IEEE Trans. Very Large Scale Integr. Syst. 17 (11) (2009)
Lih-Yih Chiou, Shien-Chun Luo
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. ISCAS (2007)
Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang
Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. ISCAS (2006)
Meng-Fan Chang, Lih-Yih Chiou, Kuei-Ann Wen
A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique. IEEE J. Solid State Circuits 41 (2) (2006)
Meng-Fan Chang, Lih-Yih Chiou, Kuei-Ann Wen
Crosstalk-insensitive via-programming ROMs using content-aware design framework. IEEE Trans. Circuits Syst. II Express Briefs (6) (2006)
Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
Synthesis of application-specific highly efficient multi-mode cores for embedded systems. ACM Trans. Embed. Comput. Syst. 4 (1) (2005)
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. ICASSP (5) (2004)
Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. DATE (2003)
Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. Very Large Scale Integr. Syst. 10 (1) (2002)
Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications. VLSI Design 2001 (2) (2001)
Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy
DSP data path synthesis for low-power applications. ICASSP (2001)