Jongsun Park

ORCID

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 87

Top Venues

ISOCC

DAC

IEEE Trans. Very Large Scale Integr. Syst.

ISCAS

Publications

Joongho Jo, Hyeongwon Kim, Jongsun Park
Identifying Unnecessary 3D Gaussians using Clustering for Fast Rendering of 3D Gaussian Splatting. CoRR (2024)
Kyeongho Lee, Joonhyung Kim, Jongsun Park
A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations. IEEE J. Solid State Circuits 59 (6) (2024)
Junhyun Song, Kyeongho Lee, Jongsun Park
Low Area and Low Power Threshold Implementation Design Technique for AES S-Box. IEEE Trans. Circuits Syst. II Express Briefs 70 (3) (2023)
Joongho Jo, Geonho Kim, Seungtae Kim, Jongsun Park
LoCoExNet: Low-Cost Early Exit Network for Energy Efficient CNN Accelerator Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (12) (2023)
Sungsoo Cheon, Kyeongho Lee, Jongsun Park
A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (5) (2023)
Dongyeob Shin, Geonho Kim, Joongho Jo, Jongsun Park
Low Complexity Gradient Computation Techniques to Accelerate Deep Neural Network Training. IEEE Trans. Neural Networks Learn. Syst. 34 (9) (2023)
Dongwoo Lew, Kyungchul Lee, Jongsun Park
A time-to-first-spike coding and conversion aware training for energy-efficient deep spiking neural network processor design. DAC (2022)
Dongsu Kim, Yunho Jang, Taehwan Kim, Jongsun Park
BiMDiM: Area efficient Bi-directional MRAM Digital in-Memory Computing. AICAS (2022)
Yunho Jang, Jongsun Park
Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing With Adjacent Cells. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Joongho Jo, Jongsun Park
Class Difficulty based Mixed Precision Quantization for Low Complexity CNN Training. ISOCC (2022)
Dongwoo Lew, Jongsun Park
A Layer-wise Training and Pruning Method for Memory Efficient On-chip Learning Hardware. ISOCC (2022)
Taehwan Kim, Yunho Jang, Min-Gu Kang, Byong-Guk Park, Kyung-Jin Lee, Jongsun Park
SOT-MRAM Digital PIM Architecture With Extended Parallelism in Matrix Multiplication. IEEE Trans. Computers 71 (11) (2022)
Sunghyun Choi, Dongwoo Lew, Jongsun Park
Early Termination Based Training Acceleration for an Energy-Efficient SNN Processor Design. IEEE Trans. Biomed. Circuits Syst. 16 (3) (2022)
Joonhyung Kim, Kyeongho Lee, Jongsun Park
A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. ISLPED (2022)
Kyeongho Lee, Joonhyung Kim, Jongsun Park
Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion. ICCAD (2022)
Joonhyung Kim, Kyeongho Lee, Jongsun Park
A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. CoRR (2022)
Dongwoo Lew, Kyungchul Lee, Jongsun Park
A Time-to-first-spike Coding and Conversion Aware Training for Energy-Efficient Deep Spiking Neural Network Processor Design. CoRR (2022)
Kyungchul Lee, Jongsun Park
Clipped Quantization Aware Training for Hardware Friendly Implementation of Image Classification Networks. ISOCC (2022)
Jooyoon Kim, Yunho Jang, Taehwan Kim, Jongsun Park
A Dual-Domain Dynamic Reference Sensing for Reliable Read Operation in SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (5) (2022)
Yunho Jang, Gyuseong Kang, Taehwan Kim, Yeongkyo Seo, Kyung-Jin Lee, Byong-Guk Park, Jongsun Park
Stochastic SOT Device Based SNN Architecture for On-Chip Unsupervised STDP Learning. IEEE Trans. Computers 71 (9) (2022)
Seunghwan Bang, Dongwoo Lew, Sunghyun Choi, Jongsun Park
An Energy-Efficient SNN Processor Design based on Sparse Direct Feedback and Spike Prediction. IJCNN (2021)
Kyeongho Lee, Woong Choi, Jongsun Park
A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge. IEEE J. Solid State Circuits 56 (8) (2021)
Kyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong Choi, Jongsun Park
A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration. DAC (2021)
Junhyun Song, Junghoon Cho, Jongsun Park
Key Length Reconfigurable ARIA Hardware with S-box Optimization. ICEIC (2021)
Junghoon Cho, Junhyun Song, Jongsun Park
Low Cost Heterogeneous ARIA S-Box Implementation for CPA-Resistance. ISCAS (2021)
Nahsung Kim, Dongyeob Shin, Wonseok Choi, Geonho Kim, Jongsun Park
Exploiting Retraining-Based Mixed-Precision Quantization for Low-Cost DNN Accelerator Design. IEEE Trans. Neural Networks Learn. Syst. 32 (7) (2021)
Daehan Ji, Dongyeob Shin, Jongsun Park
An Error Compensation Technique for Low-Voltage DNN Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Jinho Jeong, Dongyeob Shin, Wongyu Shin, Jongsun Park
An Even/Odd Error Detection Based Low-Complexity Chase Decoding for Low-Latency RS Decoder Design. IEEE Commun. Lett. 25 (5) (2021)
Hoyoung Tang, Donghyeon Cho, Dongwoo Lew, Taehwan Kim, Jongsun Park
Rank order coding based spiking convolutional neural network architecture with energy-efficient membrane voltage updates. Neurocomputing 407 (2020)
Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. DAC (2020)
Junghoon Cho, Junhyun Song, Jongsun Park
Implementation of Low Cost ARIA Architecture with Composite Field Optimization and Datapath Modification. ISOCC (2020)
Heetak Kim, Hoyoung Tang, Woong Choi, Jongsun Park
An Energy-Quality Scalable STDP Based Sparse Coding Processor With On-Chip Learning Capability. IEEE Trans. Biomed. Circuits Syst. 14 (1) (2020)
Dongyeob Shin, Geonho Kim, Joongho Jo, Jongsun Park
Prediction Confidence based Low Complexity Gradient Computation for Accelerating DNN Training. DAC (2020)
Taehwan Kim, Eunjong Yeo, Yunho Jang, Yeongkyo Seo, Jongsun Park
Dynamic-Reference Based Early Write Termination for Low Energy SOT-MRAM. ISCAS (2020)
Sunghyun Choi, Jongsun Park
Early Termination of STDP Learning with Spike Counts in Spiking Neural Networks. ISOCC (2020)
Joongho Jo, Jongsun Park
Confidence Score based Mini-batch Skipping for CNN Training on Mini-batch Training Environment. ISOCC (2020)
Jinil Chung, Woong Choi, Jongsun Park, Swaroop Ghosh
Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers. IEEE Access 8 (2020)
Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. CoRR (2020)
Sungsoo Cheon, Jongsun Park
A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance. ISOCC (2020)
Geonho Kim, Jongsun Park
Low Cost Early Exit Decision Unit Design for CNN Accelerator. ISOCC (2020)
Jinho Jeong, Jongsun Park
Fast 6T SRAM Bit-Line Computing with Consecutive Short Pulse Word-Lines and Skewed Inverter. ISOCC (2020)
Hoyoung Tang, Heetak Kim, Hyeonseong Kim, Jongsun Park
Spike Counts Based Low Complexity SNN Architecture With Binary Synapse. IEEE Trans. Biomed. Circuits Syst. 13 (6) (2019)
Gyuseong Kang, Jongsun Park
Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM. IEEE Trans. Very Large Scale Integr. Syst. 27 (6) (2019)
Wonseok Choi, Dongyeob Shin, Jongsun Park, Swaroop Ghosh
Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators. DAC (2019)
Bohun Kim, Junghoon Cho, Byungjun Choi, Jongsun Park, Hwajeong Seo
Compact Implementations of HIGHT Block Cipher on IoT Platforms. Secur. Commun. Networks 2019 (2019)
Won Jun Lee, Chang Hyun Kim, Yoonah Paik, Jongsun Park, Il Park, Seon Wook Kim
Design of Processing-"Inside"-Memory Optimized for DRAM Behaviors. IEEE Access 7 (2019)
Kyeongho Lee, Geon Ko, Jongsun Park
Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme. ISCAS (2019)
Seyedhamidreza Motaman, Swaroop Ghosh, Jongsun Park
A Perspective on Test Methodologies for Supervised Machine Learning Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (3) (2019)
Dongyeob Shin, Wonseok Choi, Jongsun Park, Swaroop Ghosh
Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (3) (2019)
Heetak Kim, Hoyoung Tang, Jongsun Park
An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding. ISLPED (2019)
Cheolhwan Kim, Dongyeob Shin, Bohun Kim, Jongsun Park
Mosaic-CNN: A Combined Two-Step Zero Prediction Approach to Trade off Accuracy and Computation Energy in Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (4) (2018)
Taehwan Kim, Jongsun Park
Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. ISOCC (2018)
Hoyoung Tang, Heetak Kim, Donghyeon Cho, Jongsun Park
Spike Counts Based Low Complexity Learning with Binary Synapse. IJCNN (2018)
Dongyeob Shin, Jongsun Park
A Low-Latency and Area-Efficient Gram-Schmidt-Based QRD Architecture for MIMO Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2018)
Woong Choi, Jongsun Park, Hoonki Kim, Changnam Park, Taejoong Song
Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. VLSI Circuits (2018)
Gyuseong Kang, Yunho Jang, Jongsun Park
Spin Orbit Torque Device based Stochastic Multi-bit Synapses for On-chip STDP Learning. ISLPED (2018)
Juseong Lee, Hoyoung Tang, Jongsun Park
Energy Efficient Canny Edge Detector for Advanced Mobile Vision Applications. IEEE Trans. Circuits Syst. Video Technol. 28 (4) (2018)
Woong Choi, Kyeongho Lee, Jongsun Park
Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. ISCAS (2018)
Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park
Content addressable memory based binarized neural network accelerator using time-domain signal processing. DAC (2018)
Woong Choi, Kyungrak Choi, Jongsun Park
Low Cost Convolutional Neural Network Accelerator Based on Bi-Directional Filtering and Bit-Width Reduction. IEEE Access 6 (2018)
Gyuseong Kang, Yunho Jang, Jongsun Park
Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM. ISCAS (2018)
Byeonggil Park, Jongsun Park, Youngjoo Lee
Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions. IEEE Access 6 (2018)
Byungjun Choi, Bohun Kim, Jongsun Park
Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique. ISOCC (2018)
Wonseok Choi, Jongsun Park
An efficient convolutional neural networks design with heterogeneous SRAM cell sizing. ISOCC (2017)
Qianying Tang, Chen Zhou, Woong Choi, Gyuseong Kang, Jongsun Park, Keshab K. Parhi, Chris H. Kim
Challenge Response Pairs per 1Kbit array for secure chip authentication. CICC (2017)
Dongyeob Shin, Jongsun Park, Jangwon Park, Somnath Paul, Swarup Bhunia
Adaptive ECC for Tailored Protection of Nanoscale Memory. IEEE Des. Test 34 (6) (2017)
Asmit De, Mohammad Nasim Imtiaz Khan, Jongsun Park, Swaroop Ghosh
Replacing eFlash with STTRAM in IoTs: Security Challenges and Solutions. J. Hardw. Syst. Secur. 1 (4) (2017)
Woong Choi, Jongsun Park
Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (9) (2017)
Kyungrak Choi, Woong Choi, Kyungho Shin, Jongsun Park
Bit-width reduction and customized register for low cost convolutional neural network accelerator. ISLPED (2017)
Byeonggil Park, Seungyong An, Jongsun Park, Youngjoo Lee
Novel Folded-KES Architecture for High-Speed and Area-Efficient BCH Decoders. IEEE Trans. Circuits Syst. II Express Briefs (5) (2017)
Kyungho Shin, Woong Choi, Jongsun Park
Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2017)
Gyuseong Kang, Woong Choi, Jongsun Park
Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar
Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (3) (2016)
Chan-Keun Kwon, Hoon Ki Kim, Jongsun Park, Soo-Won Kim
A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Hoyoung Tang, Jongsun Park
Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Woong Choi, Jongsun Park
A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2016)
Jinil Chung, Jongsun Park, Swaroop Ghosh
Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency. ISLPED (2016)
Sangkyu Lee, Hoyoung Tang, Kyungrak Choi, Jongsun Park
Customized SRAM design for low power video code applications. ISOCC (2016)
Sandip Ray, Jongsun Park, Swarup Bhunia
Wearables, Implants, and Internet of Things: The Technology Needs in the Evolving Landscape. IEEE Trans. Multi Scale Comput. Syst. 2 (2) (2016)
Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh
Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2016)
Gihoon Jung, Kyungrak Choi, Jongsun Park
A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method. APCCAS (2016)
Hoyoung Tang, Gihoon Jung, Jongsun Park
A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. ISCAS (2015)
Sandip Ray, Jongsun Park, Swarup Bhunia
Guest Editors' Introduction: Wearables, Implants, and Internet of Things. IEEE Trans. Multi Scale Comput. Syst. 1 (2) (2015)
Jae-Won Jang, Jongsun Park, Swaroop Ghosh, Swarup Bhunia
Self-correcting STTRAM under magnetic field attacks. DAC (2015)
Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh
Domain wall memory based digital signal processors for area and energy-efficiency. DAC (2015)
Woong Choi, Gyuseong Kang, Jongsun Park
A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder. IEEE J. Solid State Circuits 50 (10) (2015)
Joon Goo Lee, Seon Wook Kim, Dong-Hyun Kim, Younga Cho, Jae-Sung Rieh, Gyusung Kang, Jongsun Park, Hokyu Lee, Sejin Park, Chulwoo Kim
ART: Direct Data Accessing from Passive RFID Tag for infra-less, contact-less, and battery-less pervasive computing. Microprocess. Microsystems 39 (8) (2015)
Ji-Hwan Yoon, Jongsun Park
An Efficient Memory-Address Remapping Technique for High-Throughput QC-LDPC Decoder. Circuits Syst. Signal Process. 33 (11) (2014)
Ji-Hwan Yoon, Dongyeob Shin, Jongsun Park
A low-complexity composite QR decomposition architecture for MIMO detector. ISCAS (2014)
Jangwon Park, Jongsun Park, Swarup Bhunia
VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications. IEEE Trans. Circuits Syst. II Express Briefs (2) (2014)
Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority. IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Anandaroop Ghosh, Somnath Paul, Jongsun Park, Swarup Bhunia
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Iput Heri Kurniawan, Ji-Hwan Yoon, Jongsun Park
Multidimensional Householder based high-speed QR decomposition architecture for MIMO receivers. ISCAS (2013)
Insoo Lee, Jinmo Kwon, Jangwon Park, Jongsun Park
Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System. J. Signal Process. Syst. 73 (2) (2013)
Abhishek Basak, Somnath Paul, Jangwon Park, Jongsun Park, Swarup Bhunia
Reconfigurable ECC for adaptive protection of memory. MWSCAS (2013)
Young-Jae Min, Hoon Ki Kim, Yu-Ri Kang, Gil-Su Kim, Jongsun Park, Soo-Won Kim
Design of Wavelet-Based ECG Detector for Implantable Cardiac Pacemakers. IEEE Trans. Biomed. Circuits Syst. 7 (4) (2013)
Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip. IEEE Trans. Very Large Scale Integr. Syst. 21 (1) (2013)
Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park
High-speed tournament givens rotation-based QR Decomposition Architecture for MIMO Receiver. ISCAS (2012)
Phi-Hung Pham, Jongsun Park, Phuong Mau, Chulwoo Kim
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 20 (2) (2012)
Woojin Rim, Woong Choi, Jongsun Park
Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics. IEEE Trans. Circuits Syst. II Express Briefs (9) (2012)

Jongsun Park.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Jongsun Park