Low Area and Low Power Threshold Implementation Design Technique for AES S-Box.
Junhyun SongKyeongho LeeJongsun ParkPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2023)
Keyphrases
- low power
- low power consumption
- vlsi architecture
- s box
- single chip
- cmos technology
- high speed
- low cost
- power consumption
- advanced encryption standard
- logic circuits
- block cipher
- gate array
- digital signal processing
- ultra low power
- design methodology
- vlsi implementation
- design process
- efficient implementation
- power dissipation
- real time
- mixed signal
- vlsi circuits
- analog to digital converter