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A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations.
Kyeongho Lee
Joonhyung Kim
Jongsun Park
Published in:
IEEE J. Solid State Circuits (2024)
Keyphrases
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dynamic random access memory
power consumption
random access memory
low power
cmos technology
design process
nm technology
case study
memory hierarchy
power reduction
operating system
high speed
memory requirements
data transmission
low cost
embedded dram
database systems