Rajiv V. Joshi

ORCID

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 66

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

CICC

AICAS

ISQED

Publications

Sumit Diware, Koteswararao Chilakala, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks. IEEE Access 12 (2024)
Sumit Diware, Mohammad Amin Yaldagard, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks. AICAS (2024)
Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS (2024)
Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS (2024)
Zijian Zhao, Sola Woo, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Zhouhang Jiang, Shan Deng, Yi Xiao, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Steven Soss, Sven Beyer, Rajiv V. Joshi, Scott Meninger, Mohamed Mohamed, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Suman Datta, Shimeng Yu, Kai Ni
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate. CoRR (2024)
Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED (2024)
Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi
A Best Balance Ratio Ordered Feature Selection Methodology for Robust and Fast Statistical Analysis of Memory Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (6) (2023)
Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID (2023)
Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET. CoRR (2023)
Rajiv V. Joshi, Sudipto Chakraborty
(Invited) Predictive analytics for cryogenic CMOS in future quantum computing systems. DAC (2023)
Abhairaj Singh, Rajendra Bishnoi, Ali Kaichouhi, Sumit Diware, Rajiv V. Joshi, Said Hamdioui
Computation-in-Memory using Ring-Oscillator based ADC for Edge AI. AICAS (2023)
Sumit Diware, Abhairaj Singh, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks. IEEE Trans. Emerg. Top. Comput. Intell. 7 (1) (2023)
Mohammad Amin Yaldagard, Sumit Diware, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture. AICAS (2023)
Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS (2023)
David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Chris Baks, John Timmerwilke, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
Low power cryogenic RF ASICs for quantum computing. CICC (2023)
Sumit Diware, Sudeshna Dash, Anteneh Gebregiorgis, Rajiv V. Joshi, Christos Strydis, Said Hamdioui, Rajendra Bishnoi
Severity-Based Hierarchical ECG Classification Using Neural Networks. IEEE Trans. Biomed. Circuits Syst. 17 (1) (2023)
Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman
Cryogenic CMOS: design considerations for future quantum computing systems. CICC (2023)
Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
Mapping-aware Biased Training for Accurate Memristor-based Neural Networks. AICAS (2023)
Abhairaj Singh, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
Referencing-in-Array Scheme for RRAM-based CIM Architecture. DATE (2022)
David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. ISSCC (2022)
Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS (2022)
Mahta Mayahinia, Abhairaj Singh, Christopher Bengel, Stefan Wiefels, Muath Abu Lebdeh, Stephan Menzel, Dirk J. Wouters, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs. ACM J. Emerg. Technol. Comput. Syst. 18 (2) (2022)
Rajiv V. Joshi, John Timmerwilke, Kevin Tien, Mark Yeck, Sudipto Chakraborty
A 0.31V Vmin Cryogenic SRAM in 14 nm FinFET for Quantum Computing. VLSI Technology and Circuits (2022)
Sudipto Chakraborty, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. IEEE J. Solid State Circuits 57 (11) (2022)
Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Ali Chehab
Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Jeffrey Prinzie, Sudipto Chakraborty, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
Phase Noise Analysis of Separately Driven Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Gokul Krishnan, Li Yang, Jingbo Sun, Jubin Hazra, Xiaocong Du, Maximilian Liehr, Zheng Li, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Yu Cao
Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration. IEEE Trans. Computers 71 (11) (2022)
Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Dünkel, Steven Soss, Sven Beyer, Rajiv V. Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni
Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window. VLSI Technology and Circuits (2022)
Abhairaj Singh, Mahdi Zahedi, Taha Shahroodi, Mohit Gupta, Anteneh Gebregiorgis, Manu Komalan, Rajiv V. Joshi, Francky Catthoor, Rajendra Bishnoi, Said Hamdioui
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out. AICAS (2022)
Abhairaj Singh, Moritz Fieback, Rajendra Bishnoi, Filip Bradaric, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui
Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT. ITC (2022)
Neeraj Mishra, Lalit Mohan Dani, S. Chakraborty, Rajiv V. Joshi, Anand Bulusu
Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs. IEEE Trans. Circuits Syst. II Express Briefs 69 (1) (2022)
Kevin Tien, Ken Inoue, Scott Lekuch, David J. Frank, Sudipto Chakraborty, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. DATE (2022)
Yixin Xu, Zijian Zhao, Yi Xiao, Tongguang Yu, Halid Mulaosmanovic, Dominik Kleimaier, Stefan Dünkel, Sven Beyer, Xiao Gong, Rajiv V. Joshi, X. Sharon Hu, Shixian Wen, Amanda Sofie Rios, Kiran Lekkala, Laurent Itti, Eric Homan, Sumitha George, Vijaykrishnan Narayanan, Kai Ni
Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines. CoRR (2022)
Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang, Jian Meng, Maximilian Liehr, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-Sun Seo, Yu Cao
Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Abhairaj Singh, Sumit Diware, Anteneh Gebregiorgis, Rajendra Bishnoi, Francky Catthoor, Rajiv V. Joshi, Said Hamdioui
Low-Power Memristor-Based Computing for Edge-AI Applications. ISCAS (2021)
Gokul Krishnan, Jingbo Sun, Jubin Hazra, Xiaocong Du, Maximilian Liehr, Zheng Li, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao
Robust RRAM-based In-Memory Computing in Light of Model Stability. IRPS (2021)
Abhairaj Singh, Muath Abu Lebdeh, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (5) (2021)
Alexander Fritsch, Rajiv V. Joshi, Sudipto Chakraborty, Holger Wetter, Uma Srinivasan, Matthew Hyde, Otto A. Torreiter, Michael Kugel, Dan Radko, Hyong Kim, Daniel Friedman
24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology. ISSCC (2021)
Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture. AICAS (2021)
Gouranga Charan, Jubin Hazra, Karsten Beckmann, Xiaocong Du, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao
Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation. DAC (2020)
Nandhini Chandramoorthy, Karthik Swaminathan, Martin Cochet, Arun Paidimarri, Schuyler Eldridge, Rajiv V. Joshi, Matthew M. Ziegler, Alper Buyuktosunoglu, Pradip Bose
Resilient Low Voltage Accelerators for High Energy Efficiency. HPCA (2019)
Insik Yoon, Malik Aqeel Anwar, Rajiv V. Joshi, Titash Rakshit, Arijit Raychowdhury
Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (3) (2019)
Matthew M. Ziegler, Krishnan Kailas, Xin Zhang, Rajiv V. Joshi
Research From the IEEE IBM AI Compute and Emerging Technology Symposia. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (3) (2019)
Rajiv V. Joshi, Matthew M. Ziegler
Low Power Design From Moore to AI for nm Era : Invited Paper. MIXDES (2019)
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Maria Malik, Katayoun Neshatpour, Setareh Rafatirad, Rajiv V. Joshi, Tinoosh Mohsenin, Hassan Ghasemzadeh, Houman Homayoun
Big vs little core for energy-efficient Hadoop computing. J. Parallel Distributed Comput. 129 (2019)
Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi
Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs. ISCAS (2019)
Maria Malik, Rajiv V. Joshi, Rouwaida Kanj, Shupeng Sun, Houman Homayoun, Tong Li
Sparse Regression Driven Mixture Importance Sampling for Memory Design. IEEE Trans. Very Large Scale Integr. Syst. 26 (1) (2018)
Rajiv V. Joshi, Matthew M. Ziegler, Karthik Swaminathan, Nandhini Chandramoorthy
Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications. CICC (2018)
Krishnendu Chakrabarty, Massimo Alioto, Rajiv V. Joshi
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (9) (2017)
Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter
A Low Voltage SRAM Using Resonant Supply Boosting. IEEE J. Solid State Circuits 52 (3) (2017)
Adam Issa, Rouwaida Kanj, Ali Chehab, Rajiv V. Joshi
Yield and energy tradeoffs of an NVLatch design using radial sampling. ICICDT (2017)
Muhammad M. Khellah, Rajiv V. Joshi
Session 5 - Memory for emerging applications. CICC (2017)
Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler
Very Low Voltage (VLV) Design. ICCD (2017)
Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Maria Malik, Ali Chehab
Regularized logistic regression for fast importance sampling based SRAM yield analysis. ISQED (2017)
Leibin Ni, Hantao Huang, Zichuan Liu, Rajiv V. Joshi, Hao Yu
Distributed In-Memory Computing on Binary RRAM Crossbar. ACM J. Emerg. Technol. Comput. Syst. 13 (3) (2017)
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Rajiv V. Joshi, Matthew M. Ziegler
Programmable supply boosting techniques for near threshold and wide operating voltage SRAM. CICC (2017)
Rajiv V. Joshi, Sudesh Saroop, Rouwaida Kanj, Yang Liu, Weike Wang, Carl Radens, Yue Tan, Karthik Yogendra
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Mohamed Baker Alawieh, Fa Wang, Rouwaida Kanj, Xin Li, Rajiv V. Joshi
Efficient analog circuit optimization using sparse regression and error margining. ISQED (2016)
Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar
Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (3) (2016)
Katayoun Neshatpour, Arezou Koohi, Farnoud Farahmand, Rajiv V. Joshi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun
Big biomedical image processing hardware acceleration: A case study for K-means and image filtering. ISCAS (2016)
Maria Malik, Avesta Sasan, Rajiv V. Joshi, Setareh Rafatirah, Houman Homayoun
Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations. ISPASS (2016)
Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li
Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (3) (2016)
Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li
Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 6 (2) (2016)
Rajiv V. Joshi, Rouwaida Kanj
Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction". IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan
14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation. VLSIC (2015)
Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Enes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li, Yiran Chen
A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. DAC (2014)
Subhasish Mitra, Pradip Bose, Eric Cheng, Chen-Yong Cher, Hyungmin Cho, Rajiv V. Joshi, Young Moon Kim, Charles R. Lefurgy, Yanjing Li, Kenneth P. Rodbell, Kevin Skadron, James H. Stathis, Lukasz G. Szafaryn
The resilience wall: Cross-layer solution strategies. VLSI-DAT (2014)
Keunwoo Kim, Rouwaida Kanj, Rajiv V. Joshi
Impact of FinFET technology for power gating in nano-scale design. ISQED (2014)
Takamaro Kikkawa, Rajiv V. Joshi
Design technology co-optimization for 10 nm and beyond. CICC (2014)
Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. CICC (2014)
Gerard Touma, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab
Robust bias temperature instability refresh design and methodology for memory cell recovery. ICICDT (2014)
Sabine Francis, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab
Statistical methodology for modeling non-IID memory fails events. ISQED (2014)
Mark M. Budnik, Rasit Onur Topaloglu, Pallab Chatterjee, Keith A. Bowman, Kamesh V. Gadepally, Paul Wesling, Syed M. Alam, Rajiv V. Joshi
Welcome to ISQED 2013. ISQED (2013)
Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (1) (2013)
Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
Rajiv V. Joshi, Rouwaida Kanj, S. Butt, Emrah Acar, D. Lea, D. Sciacca
Hardware-corroborated Variability-Aware SRAM Methodology. VLSI Design (2013)
Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif
Yield estimation via multi-cones. DAC (2012)
John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC (2012)
Rouwaida Kanj, Rajiv V. Joshi
A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability. ISQED (2012)
Peiyuan Wang, Wei Zhang, Rajiv V. Joshi, Rouwaida Kanj, Yiran Chen
A thermal and process variation aware MTJ switching model and its applications in soft error analysis. ICCAD (2012)
Rajiv V. Joshi, Rouwaida Kanj, Vinod Ramadurai
A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Rajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Li
Universal statistical cure for predicting memory loss. ICCAD (2011)
Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
The Impact of Statistical Leakage Models on Design Yield Estimation. VLSI Design 2011 (2011)
J. Sujatha, Rajshri Jobanputra, Rajiv V. Joshi
A Tutorial on Enhancing the Level-of-Learning through ICT-Enabled Teaching in Engineering Education. T4E (2011)
Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif
Accelerated statistical simulation via on-demand Hermite spline interpolations. ICCAD (2011)
Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj
FinFET SRAM Design. VLSI Design (2010)
Rajiv V. Joshi, Rouwaida Kanj, Anthony Pelella, Arthur Tuminaro, Yuen H. Chan
The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane. IEEE Des. Test Comput. 27 (6) (2010)
Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. ISLPED (2010)
Jeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv V. Joshi, Rouwaida Kanj
Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test. ISQED (2010)
Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi
The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED (2009)
Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Yue Tan
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. IEEE J. Solid State Circuits 44 (3) (2009)
Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka
Statistical yield analysis of silicon-on-insulator embedded DRAM. ISQED (2009)
Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. ICCAD (2009)
Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED (2008)
Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif
A Root-Finding Method for Assessing SRAM Stability. ISQED (2008)
Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang
Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. ISQED (2008)

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Rajiv V. Joshi