Don Plass

Publication Activity (10 Years)

Years Active: 2000-2012
Publications (10 Years): 0

Top Venues

Publications

John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC (2012)
John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Caon
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. IEEE J. Solid State Circuits 46 (1) (2011)
John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, N. Cao
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. ISSCC (2010)
Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. ESSCIRC (2008)
John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. ISSCC (2006)
Doug Malone, Paul Bunce, Joe DellaPietro, John Davis, James Dawson, Thomas J. Knips, Don Plass, Phil Pritzlaff, Kenneth Reyer
Design validation of .18 μm 1 GHz cache and register arrays. CICC (2000)