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Paul Bunce
Publication Activity (10 Years)
Years Active: 1992-2013
Publications (10 Years): 0
Top Topics
Shared Memory Multiprocessors
Embedded Dram
Dynamic Random Access Memory
Multithreading
Top Venues
ISSCC
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Publications
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John Davis
,
Paul Bunce
,
Diana M. Henderson
,
Yuen H. Chan
,
Uma Srinivasan
,
Daniel Rodko
,
Pradip Patel
,
Thomas J. Knips
,
Tobias Werner
7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor.
ISSCC
(2013)
James D. Warnock
,
Yiu-Hing Chan
,
Sean M. Carey
,
Huajun Wen
,
Patrick J. Meaney
,
Guenter Gerwig
,
Howard H. Smith
,
Yuen H. Chan
,
John Davis
,
Paul Bunce
,
Antonio Pelella
,
Daniel Rodko
,
Pradip Patel
,
Thomas Strach
,
Doug Malone
,
Frank Malgioglio
,
José Neves
,
David L. Rude
,
William V. Huott
Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System.
IEEE J. Solid State Circuits
47 (1) (2012)
John Davis
,
Don Plass
,
Paul Bunce
,
Yuen H. Chan
,
Antonio Pelella
,
Rajiv V. Joshi
,
A. Chen
,
William V. Huott
,
Thomas J. Knips
,
Pradip Patel
,
K. Lo
,
Eric Fluhr
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor.
ISSCC
(2006)
Doug Malone
,
Paul Bunce
,
Joe DellaPietro
,
John Davis
,
James Dawson
,
Thomas J. Knips
,
Don Plass
,
Phil Pritzlaff
,
Kenneth Reyer
Design validation of .18 μm 1 GHz cache and register arrays.
CICC
(2000)
Paul Bunce
,
William Chin
,
Leo Clark
,
Barry Krumm
Directory and Trace memory chip with active discharge cell.
IBM J. Res. Dev.
36 (5) (1992)