John Barth

Publication Activity (10 Years)

Years Active: 1998-2012
Publications (10 Years): 0

Top Venues

Publications

John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC (2012)
Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. ICICDT (2012)
John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Caon
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. IEEE J. Solid State Circuits 46 (1) (2011)
John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, N. Cao
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. ISSCC (2010)
Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits 44 (4) (2009)
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43 (1) (2008)
Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. ESSCIRC (2008)
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC (2007)
Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits 38 (11) (2003)
Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek
Embedded DRAM built in self test and methodology for test insertion. ITC (2001)
Jeffrey H. Dreibelbis, John Barth, Howard L. Kalter, Rex Kho
Processor-based built-in self-test for embedded DRAM. IEEE J. Solid State Circuits 33 (11) (1998)