A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
John BarthWilliam R. ReohrPaul C. ParriesGregory FredemanJohn GolzStanley SchusterRichard E. MatickHillery C. HunterCharles TannerJoseph HarigHoki KimBabar A. KhanJohn GriesemerRobert HavrelukKenji YanagisawaToshiaki KirihataSubramanian S. IyerPublished in: ISSCC (2007)