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A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.

John BarthWilliam R. ReohrPaul C. ParriesGregory FredemanJohn GolzStanley SchusterRichard E. MatickHillery C. HunterCharles TannerJoseph HarigHoki KimBabar A. KhanJohn GriesemerRobert HavrelukKenji YanagisawaToshiaki KirihataSubramanian S. Iyer
Published in: ISSCC (2007)
Keyphrases
  • cmos technology
  • high speed
  • embedded dram
  • dynamic random access memory
  • dynamic range
  • silicon on insulator
  • random access memory
  • response time
  • operating system