Hillery C. Hunter

Publication Activity (10 Years)

Years Active: 2000-2020
Publications (10 Years): 4

Top Topics

Emerging Technologies

Ibm Zenterprise

Memory Subsystem

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

IBM J. Res. Dev.

Publications

Saravanan Sethuraman, Venkata Kalyan Tavva, Karthick Rajamani, Chitra K. Subramanian, Kyu-hyoun Kim, Hillery C. Hunter, M. B. Srinivas
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Minsik Cho, Ulrich Finkler, Mauricio J. Serrano, David S. Kung, Hillery C. Hunter
BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy. IBM J. Res. Dev. 63 (6) (2019)
Minsik Cho, Ulrich Finkler, David S. Kung, Hillery C. Hunter
BlueConnect: Decomposing All-Reduce for Deep Learning on Heterogeneous Network Hierarchy. MLSys (2019)
Grigori Fursin, Thierry Moreau, Hillery C. Hunter, Yiran Chen, Charles Qi, Tianqi Chen
PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research. ReQuEST@ASPLOS (2018)
Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy
Guest Editorial Computing in Emerging Technologies (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (1) (2015)
Hillery C. Hunter, Luis Alfonso Lastras-Montaño, Bishwaranjan Bhattacharjee
Adapting Server Systems for New Memory Technologies. Computer 47 (9) (2014)
Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy
Guest Editorial Computing in Emerging Technologies (First Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (4) (2014)
Janani Mukundan, Hillery C. Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. ISCA (2013)
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue. IEEE Micro 31 (1) (2011)
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory. MICRO (2010)
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John
The virtual write queue: coordinating DRAM and last-level cache policies. ISCA (2010)
Hillery C. Hunter, Erik M. Nystrom, Daniel A. Connors, Wen-mei W. Hwu
Hardware-compiler co-design for adjustable data power savings. Microprocess. Microsystems 33 (4) (2009)
Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits 44 (4) (2009)
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43 (1) (2008)
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC (2007)
Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter
An innovative low-power high-performance programmable signal processor for digital communications. IBM J. Res. Dev. 47 (2-3) (2003)
Hillery C. Hunter, Jaime H. Moreno
A new look at exploiting data parallelism in embedded systems. CASES (2003)
Hillery C. Hunter, Wen-mei W. Hwu
Code coverage and input variability: effects on architecture and compiler research. CASES (2002)
John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu
Enhancing loop buffering of media and telecommunications applications using low-overhead predication. MICRO (2001)
Daniel A. Connors, Hillery C. Hunter, Ben-Chung Cheng, Wen-mei W. Hwu
Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse. ASPLOS (2000)