A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
Peter J. KlimJohn BarthWilliam R. ReohrDavid DickGregory FredemanGary KochHien M. LeAditya KhargonekarPamela WilcoxJohn GolzJente B. KuangAbraham MathewsJethro C. LawTrong LuongHung C. NgoRyan FreeseHillery C. HunterErik NelsonPaul C. ParriesToshiaki KirihataSubramanian S. IyerPublished in: IEEE J. Solid State Circuits (2009)