Paul C. Parries

Publication Activity (10 Years)

Years Active: 2005-2018
Publications (10 Years): 1

Top Topics

Silicon On Insulator

Dynamic Random Access Memory

Top Venues

IBM J. Res. Dev.

Publications

Scott R. Stiffler, Ravikumar Ramachandran, W. Kirklen Henson, Noah D. Zamdmer, Kevin McStay, Giuseppe La Rosa, Kevin M. Boyd, Sungjae Lee, Claude Ortolland, Paul C. Parries
Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs. IBM J. Res. Dev. 62 (2/3) (2018)
G. Freeman, P. Chang, E. R. Engbrecht, K. J. Giewont, D. F. Hilscher, M. Lagus, T. J. McArdle, B. Morgenfeld, Shreesh Narasimha, James P. Norum, K. A. Nummy, Paul C. Parries, G. Wang, Jonathan K. Winslow, Paul D. Agnello, Rajeev Malik
Performance-optimized gate-first 22-nm SOI technology with embedded DRAM. IBM J. Res. Dev. 59 (1) (2015)
Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. ICICDT (2012)
Subramanian S. Iyer, Greg G. Freeman, Colin Brodsky, Anthony I. Chou, Dan Corliss, Sameer H. Jain, Naftali E. Lustig, Vincent McGahay, Shreesh Narasimha, James P. Norum, Karen A. Nummy, Paul C. Parries, Sujatha Sankaran, Chris D. Sheraw, Pushkara Rao Varanasi, Geng Wang, Mary E. Weybright, Xiaojun Yu, Emmanuel Crabbe, Paul D. Agnello
45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications. IBM J. Res. Dev. 55 (3) (2011)
Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits 44 (4) (2009)
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43 (1) (2008)
Wei Kong, Paul C. Parries, G. Wang, Subramanian S. Iyer
Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation. ITC (2008)
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC (2007)
Subramanian S. Iyer, John E. Barth Jr., Paul C. Parries, James P. Norum, James P. Rice, Lyndon R. Logan, Dennis Hoyniak
Embedded DRAM: Technology platform for the Blue Gene/L chip. IBM J. Res. Dev. 49 (2-3) (2005)
Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer
An 800-MHz embedded DRAM with a concurrent refresh mode. IEEE J. Solid State Circuits 40 (6) (2005)