Paul D. Agnello

Publication Activity (10 Years)

Years Active: 1995-2015
Publications (10 Years): 0

Top Topics

Silicon On Insulator

Random Access Memory

Top Venues

IBM J. Res. Dev.

Publications

G. Freeman, P. Chang, E. R. Engbrecht, K. J. Giewont, D. F. Hilscher, M. Lagus, T. J. McArdle, B. Morgenfeld, Shreesh Narasimha, James P. Norum, K. A. Nummy, Paul C. Parries, G. Wang, Jonathan K. Winslow, Paul D. Agnello, Rajeev Malik
Performance-optimized gate-first 22-nm SOI technology with embedded DRAM. IBM J. Res. Dev. 59 (1) (2015)
Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. ICICDT (2012)
Subramanian S. Iyer, Greg G. Freeman, Colin Brodsky, Anthony I. Chou, Dan Corliss, Sameer H. Jain, Naftali E. Lustig, Vincent McGahay, Shreesh Narasimha, James P. Norum, Karen A. Nummy, Paul C. Parries, Sujatha Sankaran, Chris D. Sheraw, Pushkara Rao Varanasi, Geng Wang, Mary E. Weybright, Xiaojun Yu, Emmanuel Crabbe, Paul D. Agnello
45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications. IBM J. Res. Dev. 55 (3) (2011)
Daniel J. Poindexter, Scott R. Stiffler, Philip T. Wu, Paul D. Agnello, Thomas Ivers, Shreesh Narasimha, Thomas B. Faure, Jed H. Rankin, David A. Grosch, Marc D. Knox, Daniel C. Edelstein, Mukesh Khare, Gary B. Bronner, Hyun-Jang Nam, Shahid A. Butt
Optimization of silicon technology for the IBM System z9. IBM J. Res. Dev. 51 (1/2) (2007)
Paul D. Agnello
Process requirements for continued scaling of CMOS-the need and prospects for atomic-level manipulation. IBM J. Res. Dev. 46 (2-3) (2002)
Randy W. Mann, Larry A. Clevenger, Paul D. Agnello, Francis R. White
Silicides and local interconnections for high-performance VLSI applications. IBM J. Res. Dev. 39 (4) (1995)