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An 800-MHz embedded DRAM with a concurrent refresh mode.

Toshiaki KirihataPaul C. ParriesDavid R. HansonHoki KimJohn GolzGregory FredemanRaj RajeevakumarJohn GriesemerNorman RobsonAlberto CesteroBabar A. KhanGeng WangMatt WordemanSubramanian S. Iyer
Published in: IEEE J. Solid State Circuits (2005)
Keyphrases
  • cmos technology
  • embedded dram
  • high speed
  • random access memory
  • data structure
  • power consumption
  • digital camera
  • power dissipation
  • dynamic random access memory