A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
John BarthWilliam R. ReohrPaul C. ParriesGregory FredemanJohn GolzStanley SchusterRichard E. MatickHillery C. HunterCharles TannerJoseph HarigHoki KimBabar A. KhanJohn GriesemerRobert HavrelukKenji YanagisawaToshiaki KirihataSubramanian S. IyerPublished in: IEEE J. Solid State Circuits (2008)