Victor V. Zyuban

Publication Activity (10 Years)

Years Active: 1998-2015
Publications (10 Years): 3

Top Topics

Power Reduction

Design Space Exploration

Top Venues

IBM J. Res. Dev.

Publications

Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits 50 (1) (2015)
Victor V. Zyuban, Peter Nilsson
Session 8 overview: Low-power digital techniques: Energy-efficient digital. ISSCC (2015)
Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. 59 (1) (2015)
Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor
processor: Designed for big data, analytics, and cloud environments. ICICDT (2014)
Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban
POWER8 design methodology innovations for improving productivity and reducing power. CICC (2014)
Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler
: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. ISSCC (2014)
Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. ICCAD (2013)
Victor V. Zyuban, Scott A. Taylor, Birger Christensen, A. R. Hall, Christopher J. Gonzalez, Joshua Friedrich, Frances Clougherty, Jon Tetzloff, Rajeev R. Rao
IBM POWER7+ design for higher frequency at fixed power. IBM J. Res. Dev. 57 (6) (2013)
Matthew M. Ziegler, George Gristede, Victor V. Zyuban
Power reduction by aggressive synthesis design space exploration. ISLPED (2013)
Michael S. Floyd, Alan J. Drake, Nicole S. Schwartz, Robert W. Berry, Charles Lefurgy, Malcolm S. Ware, Karthick Rajamani, Victor V. Zyuban, Richard L. Willaman, Ruby M. Zgabay
Runtime power reduction capability of the IBM POWER7+ chip. IBM J. Res. Dev. 57 (6) (2013)
Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits 46 (1) (2011)
Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban
Power-efficient, reliable microprocessor architectures: modeling and design methods. ACM Great Lakes Symposium on VLSI (2010)
James D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski
local clocking and clocked storage elements. ISSCC (2010)
Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, Roland Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott A. Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban
: A highly parallel and scalable multi-core high-end server processor. ISSCC (2010)
Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich
The opportunity cost of low power design: a case study in circuit tuning. ISLPED (2009)
Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). PATMOS (2009)
Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. ISCA (2008)
Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose
A Framework for Architecture-Level Lifetime Reliability Modeling. DSN (2007)
Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. ISCA (2005)
Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. HPCA (2005)
Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose
Microarchitectural techniques for power gating of execution units. ISLPED (2004)
Victor V. Zyuban, David M. Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma
Integrated Analysis of Power and Performance for Pipelined Microprocessors. IEEE Trans. Computers 53 (8) (2004)
Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno
Design methodology for semi custom processor cores. ACM Great Lakes Symposium on VLSI (2004)
Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter
An innovative low-power high-performance programmable signal processor for digital communications. IBM J. Res. Dev. 47 (2-3) (2003)
Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban
Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. 47 (2-3) (2003)
Victor V. Zyuban
Optimization of scannable latches for low energy. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
Victor V. Zyuban, Philip N. Strenski
Balancing hardware intensity in microprocessor pipelines. IBM J. Res. Dev. 47 (5-6) (2003)
Victor V. Zyuban, Stephen V. Kosonocky
Low power integrated scan-retention mechanism. ISLPED (2002)
Victor V. Zyuban
Unified architecture level energy-efficiency metric. ACM Great Lakes Symposium on VLSI (2002)
Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma
Optimizing pipelines for power and performance. MICRO (2002)
Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. PACS (2002)
Victor V. Zyuban, Philip N. Strenski
Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. ISLPED (2002)
Victor V. Zyuban, Peter M. Kogge
Inherently Lower-Power High-Performance Superscalar Architectures. IEEE Trans. Computers 50 (3) (2001)
Victor V. Zyuban, David Meltzer
Clocking strategies and scannable latches for low power appliacations. ISLPED (2001)
Victor V. Zyuban, Peter M. Kogge
Optimization of high-performance superscalar architectures for energy efficiency. ISLPED (2000)
David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro 20 (6) (2000)
Victor V. Zyuban, Peter M. Kogge
Application of STD to latch-power estimation. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Victor V. Zyuban, Peter M. Kogge
The energy complexity of register files. ISLPED (1998)