Nagu R. Dhanwada

Publication Activity (10 Years)

Years Active: 1998-2021
Publications (10 Years): 2

Top Topics

Energy Efficiency

Countermeasures

Ibm Power Processor

Top Venues

IEEE Des. Test Comput.

Publications

Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA (2021)
Arun Joseph, Spandana Rachamalla, Shashidhar Reddy, Nagu R. Dhanwada
Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis. VLSI Design (2019)
Nagu R. Dhanwada, William Rhett Davis, Jerry Frenkil
Towards a standard flow for system level power modeling. ICCAD (2014)
Arun Joseph, Nagu R. Dhanwada
Process Synchronization in Multi-core Systems Using On-Chip Memories. VLSI Design (2014)
Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. ICCAD (2013)
Nagu R. Dhanwada, David J. Hathaway, Jerry Frenkil, W. Rhett Davis, Harun Demircioglu
Leakage Power Contributor Modeling. IEEE Des. Test Comput. 29 (2) (2012)
Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer
Exploring power management in multi-core systems. ASP-DAC (2008)
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han
Performance modeling for early analysis of multi-core systems. CODES+ISSS (2007)
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED (2006)
Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri
Hierarchical constraint transformation based on genetic optimization for analog system synthesis. Integr. 39 (3) (2006)
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD (2005)
Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan
A power estimation methodology for systemC transaction level models. CODES+ISSS (2005)
Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin
Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. Des. Autom. Embed. Syst. 10 (2-3) (2005)
Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ACM Trans. Design Autom. Electr. Syst. 9 (2) (2004)
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu
Architecting voltage islands in core-based system-on-a-chip designs. ISLPED (2004)
Shyam Ramji, Nagu R. Dhanwada
Design topology aware physical metrics for placement analysis. ACM Great Lakes Symposium on VLSI (2003)
Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
SEAS: a system for early analysis of SoCs. CODES+ISSS (2003)
Alex Doboli, Nagu R. Dhanwada, Ranga Vemuri
A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems. ISCAS (2000)
Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. VLSI Design (1999)
Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. DAC (1999)
Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. DATE (1999)
Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. ISCAS (6) (1999)
Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. ASP-DAC (1999)
Nagu R. Dhanwada, Ranga Vemuri
Constraint Allocation in Analog System Synthesis. VLSI Design (1998)