Rahul M. Rao

Publication Activity (10 Years)

Years Active: 1978-2024
Publications (10 Years): 12

Top Topics

Cognitive Computing

Cluster Ensemble

Top Venues

IBM J. Res. Dev.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

George Antony, Gireesh Kumar K. M, Naiju Karim Abdul, Rahul M. Rao
Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster Balancing. DATE (2024)
Naiju Karim Abdul, George Antony, Rahul M. Rao, Suriya T. Skariah
Scan Chain Clustering and Optimization with Constrained Clustering and Reinforcement Learning. MLCAD (2022)
Rahul M. Rao, Christopher J. Gonzalez, Eric Fluhr, Abraham Mathews, Andrew Bianchi, Daniel Dreps, David Wolpert, Eric Lai, Gerald Strevig, Glen A. Wiedemeier, Philipp Salz, Ryan Kruse
POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. ISSCC (2022)
Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA (2021)
Shivani Bathla, Rahul M. Rao, Nitin Chandrachoodan
A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Ankur Shukla, Rahul M. Rao, James D. Warnock
Impact of Device Aging on Early Mode Failures in Pulsed Latches. VLSI Design (2018)
Dharshak B. S., Rahul M. Rao
A High Performance Gated Voltage Level Translator with Integrated Multiplexer. VLSI Design (2018)
Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam, Donald W. Plass, Paul Muench
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits 53 (1) (2018)
Eric J. Fluhr, Rahul M. Rao, Howard Smith, Alper Buyuktosunoglu, Ramon Bertran Monfort
IBM POWER9 circuit design and energy optimization for 14-nm technology. IBM J. Res. Dev. 62 (4/5) (2018)
Sumantra Sarkar, Ayan Biswas, Anindya Sundar Dhar, Rahul M. Rao
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. ISSCC (2017)
Arun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla
FVCAG: A framework for formal verification driven power modeling and verification. ISLPED (2016)
Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey
Virtual logic netlist: Enabling efficient RTL analysis. ISQED (2015)
Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. 59 (1) (2015)
Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. IEEE Trans. Very Large Scale Integr. Syst. 21 (9) (2013)
Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. ICCAD (2013)
Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif
Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. ETS (2013)
Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. 19 (1) (2011)
Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown
Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise. IEEE Trans. Very Large Scale Integr. Syst. 18 (1) (2010)
Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim
Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. CICC (2010)
Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectron. Reliab. 49 (6) (2009)
Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim
A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry. IEEE J. Solid State Circuits 44 (9) (2009)
Amlan Ghosh, Rahul M. Rao, Richard B. Brown
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. ISLPED (2009)
Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang
A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. ISCAS (2009)
Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown
On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. ISQED (2008)
Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS (2008)
Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim
A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement. ISSCC (2008)
Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design (2008)
Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. Very Large Scale Integr. Syst. 15 (6) (2007)
Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED (2005)
Harmander Singh Deogun, Dennis Sylvester, Rahul M. Rao, Kevin J. Nowka
Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength. SoCC (2005)
Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
Power-aware global signaling strategies. ISCAS (1) (2005)
Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. ISQED (2005)
Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
Approaches to run-time and standby mode leakage reduction in global buses. ISLPED (2004)
Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
Analysis and Optimization of Enhanced MTCMOS Scheme. VLSI Design (2004)
Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown
Efficient techniques for gate leakage estimation. ISLPED (2003)
Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD (2003)
Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
Leakage and leakage sensitivity computation for combinational circuits. ISLPED (2003)
Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. ESSCIRC (2003)
Leland B. Jackson, Donald W. Tufts, Frank K. Soong, Rahul M. Rao
Frequency estimation by linear prediction. ICASSP (1978)