Masanori Hashimoto

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 85

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IRPS

ASP-DAC

DATE

Publications

Kozo Takeuchi, Takashi Kato, Masanori Hashimoto
An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs. IRPS (2024)
Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto
Logic Locking over TFHE for Securing User Data and Algorithms. ASPDAC (2024)
Yangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto
Vulnerability Estimation of DNN Model Parameters with Few Fault Injections. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Hiromitsu Awano, Masanori Hashimoto
B2N2: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA. Integr. 89 (2023)
Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao, Masanori Hashimoto, Hao Yu
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 70 (6) (2023)
Minoru Harimaya, Ryo Shirai, Masanori Hashimoto
Toward Instant 3D Modeling: Highly Parallelizable Shape Reproduction Method for Soft Object Containing Numerous Tiny Position Trackers. IUI Companion (2023)
Ángel López García-Arias, Yasuyuki Okoshi, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
Recurrent Residual Networks Contain Stronger Lottery Tickets. IEEE Access 11 (2023)
Quan Cheng, Mingqiang Huang, Changhai Man, Ao Shen, Liuyao Dai, Hao Yu, Masanori Hashimoto
Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (10) (2023)
Kazusa Takami, Yuibi Gomi, Shin-ichiro Abe, Wang Liao, Seiya Manabe, Tetsuro Matsumoto, Masanori Hashimoto
Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons. IRPS (2023)
Chinamu Kawano, Masanori Hashimoto
Performance comparison of memristor crossbar-based analog and FPGA-based digital weight-memory-less neural networks. ICRC (2023)
Riku Iwamoto, Masanori Hashimoto
Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication. IOLTS (2023)
Masafumi Tanakal, Jaehoon Yu, Masaki Nakagawa, Naoya Tate, Masanori Hashimoto
Investigating Small Device Implementation of FRET-based Optical Reservoir Computing. MWSCAS (2022)
Toshihisa Tanaka, Ryo Shirai, Masanori Hashimoto
DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object. MWSCAS (2022)
Ryo Shirai, Masanori Hashimoto
Shape-Flexible Underwater Display System with Wirelessly Powered and Controlled Smart LEDs. IUI Companion (2022)
TaiYu Cheng, Yutaka Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Yangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto
Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections. DATE (2022)
Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann
VirtualSync+: Timing Optimization with Virtual Synchronization. CoRR (2022)
Dehua Liang, Jun Shiomi, Noriyuki Miura, Masanori Hashimoto, Hiromitsu Awano
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. IEICE Trans. Inf. Syst. (7) (2022)
Xu Bai, Naoki Banno, Makoto Miyamura, Ryusuke Nebashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation. IEEE J. Solid State Circuits 57 (7) (2022)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann
VirtualSync+: Timing Optimization With Virtual Synchronization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. BMVC (2021)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. DATE (2021)
Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. DATE (2021)
Dehua Liang, Masanori Hashimoto, Hiromitsu Awano
BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter. DATE (2021)
TaiYu Cheng, Masanori Hashimoto
Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling. ISCAS (2021)
Ryo Shirai, Yuichi Itoh, Masanori Hashimoto
Make it Trackable: An Instant Magnetic Tracking System With Coil-Free Tiny Trackers. IEEE Access 9 (2021)
Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. CoRR (2021)
Ryo Shirai, Masanori Hashimoto
Submarine LED: Wirelessly powered underwater display controlling its buoyancy. SIGGRAPH ASIA Posters (2021)
TaiYu Cheng, Yukata Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto
Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization. ASP-DAC (2021)
Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto
Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA. DATE (2020)
Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC (2020)
Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto
A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2020)
Hiromitsu Awano, Masanori Hashimoto
BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA. DATE (2020)
Ángel López García-Arias, Jaehoon Yu, Masanori Hashimoto
Low-Cost Reservoir Computing using Cellular Automata and Random Forests. ISCAS (2020)
TaiYu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto
Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training. Integr. 74 (2020)
Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Kojiro Ito, Masanori Hashimoto
Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing. ITC (2020)
Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto
Memory Efficient Training using Lookup-Table-based Quantization for Neural Network. AICAS (2020)
Wang Liao, Kojiro Ito, Yukio Mitsuyama, Masanori Hashimoto
Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs. IRPS (2020)
Shin-ichiro Abe, Tatsuhiko Sato, Junya Kuroda, Seiya Manabe, Yukinobu Watanabe, Wang Liao, Kojiro Ito, Masanori Hashimoto, Masahide Harada, Kenichi Oikawa, Yasuhiro Miyake
Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets. IRPS (2020)
Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Ryohei Shimizu, Ryo Shirai, Masanori Hashimoto
Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis. MWSCAS (2020)
Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. ASP-DAC (2020)
Jun Chen, Masanori Hashimoto
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction. ITC (2020)
Masanori Hashimoto, Wang Liao
Soft Error and Its Countermeasures in Terrestrial Environment. ASP-DAC (2020)
Toranosuke Tanio, Kouya Takeda, Jaehoon Yu, Masanori Hashimoto
Training Data Reduction using Support Vectors for Neural Networks. APSIPA (2019)
Liao Wang, Masanori Hashimoto
Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate. IEICE Trans. Electron. (4) (2019)
Wang Liao, Masanori Hashimoto, Seiya Manabe, Yukinobu Watanabe, Shin-ichiro Abe, Keita Nakano, Hayato Takeshita, Motonobu Tampo, Soshi Takeshita, Yasuhiro Miyake
Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs. IRPS (2019)
Pei Hao Chen, Ryo Shirai, Masanori Hashimoto
Coverage-scalable instant tabletop positioning system with self-localizable anchor nodes. IUI Companion (2019)
Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. CoRR (2019)
Yutaka Masuda, Masanori Hashimoto
MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2019)
Shota Fukui, Jaehoon Yu, Masanori Hashimoto
Distilling Knowledge for Non-Neural Networks. APSIPA (2019)
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, Shin-ichiro Abe, Yukinobu Watanabe
Characterizing SRAM and FF soft error rates with measurement and simulation. Integr. 69 (2019)
TaiYu Cheng, Jaehoon Yu, Masanori Hashimoto
Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier. PATMOS (2019)
Takahiro Nakayama, Masanori Hashimoto
Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2019)
Bing Li, Masanori Hashimoto, Ulf Schlichtmann
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018)
Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto
Hardware Architecture for Fast General Object Detection using Aggregated Channel Features. A-SSCC (2018)
Ryutaro Doi, Masanori Hashimoto, Takao Onoye
An analytic evaluation on soft error immunity enhancement due to temporal triplication. Int. J. Embed. Syst. 10 (1) (2018)
Yutaka Masuda, Jun Nagayama, Hirotaka Takeno, Yoshimasa Ogawa, Yoichi Momiyama, Masanori Hashimoto
Comparing voltage adaptation performance between replica and in-situ timing monitors. ICCAD (2018)
Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Masanori Hashimoto
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2018)
Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu
Interconnect Delay Analysis for RRAM Crossbar Based FPGA. ISVLSI (2018)
Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li
Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties. ISQED (2018)
Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto
A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes. NEWCAS (2018)
Takahiro Nakayama, Masanori Hashimoto
Hold violation analysis for functional test of ultra-low temperature circuits at room temperature. VLSI-DAT (2018)
Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto
Sneak path free reconfiguration of via-switch crossbars based FPGA. ICCAD (2018)
Yutaka Masuda, Takao Onoye, Masanori Hashimoto
Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10 (4) (2018)
Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. DAC (2018)
Yutaka Masuda, Masanori Hashimoto
MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. ASP-DAC (2018)
Ryutaro Doi, Masanori Hashimoto
SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA. ISVLSI (2018)
Liao Wang, Soichi Hirokawa, Ryo Harada, Masanori Hashimoto
Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V -. NEWCAS (2017)
Masanori Hashimoto, Ryo Shirai, Yuichi Itoh, Tetsuya Hirose
Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes. ASICON (2017)
Kauzki Hirosue, Shohei Ukawa, Yuichi Itoh, Takao Onoye, Masanori Hashimoto
GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction. IUI (2017)
Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto
Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node. ISCAS (2017)
Kuen-Wey Lin, Yih-Lang Li, Masanori Hashimoto
Near-future traffic evaluation based navigation for automated driving vehicles. Intelligent Vehicles Symposium (2017)
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin
Minimizing detection-to-boosting latency toward low-power error-resilient circuits. Integr. 58 (2017)
Yutaka Masuda, Takao Onoye, Masanori Hashimoto
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Yutaka Masuda, Masanori Hashimoto, Takao Onoye
Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms. IOLTS (2016)
Chih-Cheng Hsu, Mark Po-Hung Lin, Masanori Hashimoto
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits. SLIP (2016)
Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. ASP-DAC (2016)
Yutaka Masuda, Masanori Hashimoto, Takao Onoye
Critical path isolation for time-to-failure extension and lower voltage operation. ICCAD (2016)
Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL (2016)
Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye
Area efficient device-parameter estimation using sensitivity-configurable ring oscillator. ASP-DAC (2015)
Taiki Uemura, Takashi Kato, Hideya Matsuyama, Masanori Hashimoto
Impact of package on neutron induced single event upset in 20 nm SRAM. IRPS (2015)
Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye
Stochastic timing error rate estimation under process and temporal variations. ITC (2015)
Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye
Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Taiki Uemura, Takashi Kato, Hideya Matsuyama, Masanori Hashimoto
Soft error immune latch design for 20 nm bulk CMOS. IRPS (2015)
Takehiko Amaki, Masanori Hashimoto, Takao Onoye
An oscillator-based true random number generator with process and temperature tolerance. ASP-DAC (2015)
Yutaka Masuda, Masanori Hashimoto, Takao Onoye
Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise. ICCAD (2015)
Taiki Uemura, Masanori Hashimoto
Investigation of single event upset and total ionizing dose in FeRAM for medical electronic tag. IRPS (2015)
Shohei Ukawa, Tatsuya Shinada, Masanori Hashimoto, Yuichi Itoh, Takao Onoye
3D node localization from node-to-node distance information using cross-entropy method. VR (2015)
Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC (2015)
Daisuke Fukuda, Kenichi Watanabe, Yuji Kanazawa, Masanori Hashimoto
Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Miho Ueno, Masanori Hashimoto, Takao Onoye
Real-time on-chip supply voltage sensor and its application to trace-based timing error localization. IOLTS (2015)
Hiroaki Konoura, Toshihiro Kameda, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2014)
Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2014)
Daisuke Fukuda, Kenichi Watanabe, Naoki Idani, Yuji Kanazawa, Masanori Hashimoto
Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)

Masanori Hashimoto.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Masanori Hashimoto